On Sat 23 May 06:22 PDT 2020, Jonathan Marek wrote: > Other dts have nodes sorted by physical address, be consistent with that. >
This didn't apply cleanly, because we haven't yet migrated the hwlock to the yet to be approved binding and I don't have a usb node. I resolved it and applied the patch. Thanks, Bjorn > Signed-off-by: Jonathan Marek <[email protected]> > --- > arch/arm64/boot/dts/qcom/sm8250.dtsi | 176 +++++++++++++-------------- > 1 file changed, 88 insertions(+), 88 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi > b/arch/arm64/boot/dts/qcom/sm8250.dtsi > index a273b99bf1e6..bc8a14df60e5 100644 > --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi > @@ -379,6 +379,12 @@ ufs_mem_phy_lanes: lanes@1d87400 { > }; > }; > > + tcsr_mutex: hwlock@1f40000 { > + compatible = "qcom,tcsr-mutex"; > + reg = <0x0 0x01f40000 0x0 0x40000>; > + #hwlock-cells = <1>; > + }; > + > usb_1_hsphy: phy@88e3000 { > compatible = "qcom,sm8250-usb-hs-phy", > "qcom,usb-snps-hs-7nm-phy"; > @@ -559,15 +565,6 @@ usb_2_dwc3: dwc3@a800000 { > }; > }; > > - intc: interrupt-controller@17a00000 { > - compatible = "arm,gic-v3"; > - #interrupt-cells = <3>; > - interrupt-controller; > - reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ > - <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ > - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > - }; > - > pdc: interrupt-controller@b220000 { > compatible = "qcom,sm8250-pdc", "qcom,pdc"; > reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; > @@ -596,85 +593,6 @@ spmi_bus: qcom,spmi@c440000 { > #interrupt-cells = <4>; > }; > > - apps_rsc: rsc@18200000 { > - label = "apps_rsc"; > - compatible = "qcom,rpmh-rsc"; > - reg = <0x0 0x18200000 0x0 0x10000>, > - <0x0 0x18210000 0x0 0x10000>, > - <0x0 0x18220000 0x0 0x10000>; > - reg-names = "drv-0", "drv-1", "drv-2"; > - interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; > - qcom,tcs-offset = <0xd00>; > - qcom,drv-id = <2>; > - qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, > - <WAKE_TCS 3>, <CONTROL_TCS 1>; > - > - rpmhcc: clock-controller { > - compatible = "qcom,sm8250-rpmh-clk"; > - #clock-cells = <1>; > - clock-names = "xo"; > - clocks = <&xo_board>; > - }; > - > - rpmhpd: power-controller { > - compatible = "qcom,sm8250-rpmhpd"; > - #power-domain-cells = <1>; > - operating-points-v2 = <&rpmhpd_opp_table>; > - > - rpmhpd_opp_table: opp-table { > - compatible = "operating-points-v2"; > - > - rpmhpd_opp_ret: opp1 { > - opp-level = > <RPMH_REGULATOR_LEVEL_RETENTION>; > - }; > - > - rpmhpd_opp_min_svs: opp2 { > - opp-level = > <RPMH_REGULATOR_LEVEL_MIN_SVS>; > - }; > - > - rpmhpd_opp_low_svs: opp3 { > - opp-level = > <RPMH_REGULATOR_LEVEL_LOW_SVS>; > - }; > - > - rpmhpd_opp_svs: opp4 { > - opp-level = > <RPMH_REGULATOR_LEVEL_SVS>; > - }; > - > - rpmhpd_opp_svs_l1: opp5 { > - opp-level = > <RPMH_REGULATOR_LEVEL_SVS_L1>; > - }; > - > - rpmhpd_opp_nom: opp6 { > - opp-level = > <RPMH_REGULATOR_LEVEL_NOM>; > - }; > - > - rpmhpd_opp_nom_l1: opp7 { > - opp-level = > <RPMH_REGULATOR_LEVEL_NOM_L1>; > - }; > - > - rpmhpd_opp_nom_l2: opp8 { > - opp-level = > <RPMH_REGULATOR_LEVEL_NOM_L2>; > - }; > - > - rpmhpd_opp_turbo: opp9 { > - opp-level = > <RPMH_REGULATOR_LEVEL_TURBO>; > - }; > - > - rpmhpd_opp_turbo_l1: opp10 { > - opp-level = > <RPMH_REGULATOR_LEVEL_TURBO_L1>; > - }; > - }; > - }; > - }; > - > - tcsr_mutex: hwlock@1f40000 { > - compatible = "qcom,tcsr-mutex"; > - reg = <0x0 0x01f40000 0x0 0x40000>; > - #hwlock-cells = <1>; > - }; > - > tlmm: pinctrl@f100000 { > compatible = "qcom,sm8250-pinctrl"; > reg = <0 0x0f100000 0 0x300000>, > @@ -690,6 +608,15 @@ tlmm: pinctrl@f100000 { > wakeup-parent = <&pdc>; > }; > > + intc: interrupt-controller@17a00000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <3>; > + interrupt-controller; > + reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ > + <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > timer@17c20000 { > #address-cells = <2>; > #size-cells = <2>; > @@ -749,6 +676,79 @@ frame@17c2d000 { > }; > }; > > + apps_rsc: rsc@18200000 { > + label = "apps_rsc"; > + compatible = "qcom,rpmh-rsc"; > + reg = <0x0 0x18200000 0x0 0x10000>, > + <0x0 0x18210000 0x0 0x10000>, > + <0x0 0x18220000 0x0 0x10000>; > + reg-names = "drv-0", "drv-1", "drv-2"; > + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; > + qcom,tcs-offset = <0xd00>; > + qcom,drv-id = <2>; > + qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, > + <WAKE_TCS 3>, <CONTROL_TCS 1>; > + > + rpmhcc: clock-controller { > + compatible = "qcom,sm8250-rpmh-clk"; > + #clock-cells = <1>; > + clock-names = "xo"; > + clocks = <&xo_board>; > + }; > + > + rpmhpd: power-controller { > + compatible = "qcom,sm8250-rpmhpd"; > + #power-domain-cells = <1>; > + operating-points-v2 = <&rpmhpd_opp_table>; > + > + rpmhpd_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + rpmhpd_opp_ret: opp1 { > + opp-level = > <RPMH_REGULATOR_LEVEL_RETENTION>; > + }; > + > + rpmhpd_opp_min_svs: opp2 { > + opp-level = > <RPMH_REGULATOR_LEVEL_MIN_SVS>; > + }; > + > + rpmhpd_opp_low_svs: opp3 { > + opp-level = > <RPMH_REGULATOR_LEVEL_LOW_SVS>; > + }; > + > + rpmhpd_opp_svs: opp4 { > + opp-level = > <RPMH_REGULATOR_LEVEL_SVS>; > + }; > + > + rpmhpd_opp_svs_l1: opp5 { > + opp-level = > <RPMH_REGULATOR_LEVEL_SVS_L1>; > + }; > + > + rpmhpd_opp_nom: opp6 { > + opp-level = > <RPMH_REGULATOR_LEVEL_NOM>; > + }; > + > + rpmhpd_opp_nom_l1: opp7 { > + opp-level = > <RPMH_REGULATOR_LEVEL_NOM_L1>; > + }; > + > + rpmhpd_opp_nom_l2: opp8 { > + opp-level = > <RPMH_REGULATOR_LEVEL_NOM_L2>; > + }; > + > + rpmhpd_opp_turbo: opp9 { > + opp-level = > <RPMH_REGULATOR_LEVEL_TURBO>; > + }; > + > + rpmhpd_opp_turbo_l1: opp10 { > + opp-level = > <RPMH_REGULATOR_LEVEL_TURBO_L1>; > + }; > + }; > + }; > + }; > + > cpufreq_hw: cpufreq@18591000 { > compatible = "qcom,cpufreq-hw"; > reg = <0 0x18591000 0 0x1000>, > -- > 2.26.1 >
