On Wed, Oct 09, 2019 at 10:43:40AM +0800, JC Kuo wrote: > Add support for the XUSB pad controller found on Tegra194 SoCs. It is > mostly similar to the same IP found on Tegra186, but the number of > pads exposed differs, as do the programming sequences. Because most of > the Tegra194 XUSB PADCTL registers definition and programming sequence > are the same as Tegra186, Tegra194 XUSB PADCTL can share the same > driver, xusb-tegra186.c, with Tegra186 XUSB PADCTL. > > Tegra194 XUSB PADCTL supports up to USB 3.1 Gen 2 speed, however, it > is possible for some platforms have long signal trace that could not > provide sufficient electrical environment for Gen 2 speed. This patch > introduce a new device node property "nvidia,disable-gen2" that can > be used to specifically disable Gen 2 speed for a particular USB 3.0 > port so that the port can be limited to Gen 1 speed and avoid the > instability. > > Signed-off-by: JC Kuo <[email protected]> > --- > Changes in v4: none > Changes in v3: none > Changes in v2: > - removed unnecessary #if/#endif pairs > - introduce new soc->supports_gen2 flag which indicate whether or not > a soc supports USB 3.1 Gen 2 speed > > drivers/phy/tegra/Makefile | 1 + > drivers/phy/tegra/xusb-tegra186.c | 74 +++++++++++++++++++++++++++++++ > drivers/phy/tegra/xusb.c | 7 +++ > drivers/phy/tegra/xusb.h | 6 +++ > 4 files changed, 88 insertions(+)
Acked-by: Thierry Reding <[email protected]>
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