On Thu 2019-05-23 21:05:48, Greg Kroah-Hartman wrote:
> From: Dmitry Osipenko <[email protected]>
>
> commit 43a0541e312f7136e081e6bf58f6c8a2e9672688 upstream.
>
> Both Tegra30 and Tegra114 have 4 ASID's and the corresponding bitfield of
> the TLB_FLUSH register differs from later Tegra generations that have 128
> ASID's.
>
> In a result the PTE's are now flushed correctly from TLB and this fixes
> problems with graphics (randomly failing tests) on Tegra30.
Three copies of same code... maybe its time to introduce helper function?
> --- a/drivers/iommu/tegra-smmu.c
> +++ b/drivers/iommu/tegra-smmu.c
> @@ -102,7 +102,6 @@ static inline u32 smmu_readl(struct tegr
> #define SMMU_TLB_FLUSH_VA_MATCH_ALL (0 << 0)
> #define SMMU_TLB_FLUSH_VA_MATCH_SECTION (2 << 0)
> #define SMMU_TLB_FLUSH_VA_MATCH_GROUP (3 << 0)
> -#define SMMU_TLB_FLUSH_ASID(x) (((x) & 0x7f) << 24)
> #define SMMU_TLB_FLUSH_VA_SECTION(addr) ((((addr) & 0xffc00000) >> 12) | \
> SMMU_TLB_FLUSH_VA_MATCH_SECTION)
> #define SMMU_TLB_FLUSH_VA_GROUP(addr) ((((addr) & 0xffffc000) >> 12) | \
> @@ -205,8 +204,12 @@ static inline void smmu_flush_tlb_asid(s
> {
> u32 value;
>
> - value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) |
> - SMMU_TLB_FLUSH_VA_MATCH_ALL;
> + if (smmu->soc->num_asids == 4)
> + value = (asid & 0x3) << 29;
> + else
> + value = (asid & 0x7f) << 24;
> +
> + value |= SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_VA_MATCH_ALL;
> smmu_writel(smmu, value, SMMU_TLB_FLUSH);
> }
>
> @@ -216,8 +219,12 @@ static inline void smmu_flush_tlb_sectio
> {
> u32 value;
>
> - value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) |
> - SMMU_TLB_FLUSH_VA_SECTION(iova);
> + if (smmu->soc->num_asids == 4)
> + value = (asid & 0x3) << 29;
> + else
> + value = (asid & 0x7f) << 24;
> +
> + value |= SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_VA_SECTION(iova);
> smmu_writel(smmu, value, SMMU_TLB_FLUSH);
> }
>
> @@ -227,8 +234,12 @@ static inline void smmu_flush_tlb_group(
> {
> u32 value;
>
> - value = SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_ASID(asid) |
> - SMMU_TLB_FLUSH_VA_GROUP(iova);
> + if (smmu->soc->num_asids == 4)
> + value = (asid & 0x3) << 29;
> + else
> + value = (asid & 0x7f) << 24;
> +
> + value |= SMMU_TLB_FLUSH_ASID_MATCH | SMMU_TLB_FLUSH_VA_GROUP(iova);
> smmu_writel(smmu, value, SMMU_TLB_FLUSH);
> }
>
>
--
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