On 05/17/2019 02:53 PM, Catalin Marinas wrote:
On Fri, May 17, 2019 at 12:59:56PM -0700, Mark Salyzyn wrote:
Some (out of tree modular) drivers feel a need to ensure
data is flushed to the DDR before continuing flow.
Signed-off-by: Mark Salyzyn <[email protected]>
Cc: [email protected]
Cc: [email protected]
---
arch/arm64/mm/cache.S | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S
index a194fd0e837f..70d7cb5c0bd2 100644
--- a/arch/arm64/mm/cache.S
+++ b/arch/arm64/mm/cache.S
@@ -120,6 +120,7 @@ ENTRY(__flush_dcache_area)
dcache_by_line_op civac, sy, x0, x1, x2, x3
ret
ENDPIPROC(__flush_dcache_area)
+EXPORT_SYMBOL_GPL(__flush_dcache_area)
/*
* __clean_dcache_area_pou(kaddr, size)
NAK. Such drivers are doing something wrong, there is a dedicated
in-kernel API for that handles kernel maintenance (hint: DMA).
Thanks!
-- Mark
