Hi Arndt， -----Original Message----- From: Arnd Bergmann <[email protected]> Sent: 2019年5月17日 16:59 To: Xiaowei Bao <[email protected]> Cc: Bjorn Helgaas <[email protected]>; Rob Herring <[email protected]>; Mark Rutland <[email protected]>; Shawn Guo <[email protected]>; Leo Li <[email protected]>; Kishon <[email protected]>; Lorenzo Pieralisi <[email protected]>; gregkh <[email protected]>; M.h. Lian <[email protected]>; Mingkai Hu <[email protected]>; Roy Zang <[email protected]>; Kate Stewart <[email protected]>; Philippe Ombredanne <[email protected]>; Shawn Lin <[email protected]>; linux-pci <[email protected]>; DTML <[email protected]>; Linux Kernel Mailing List <[email protected]>; Linux ARM <[email protected]>; linuxppc-dev <[email protected]> Subject: Re: [EXT] Re: [PATCH 2/3] arm64: dts: ls1028a: Add PCIe controller DT nodes
Caution: EXT Email On Fri, May 17, 2019 at 5:21 AM Xiaowei Bao <[email protected]> wrote: > -----Original Message----- > From: Arnd Bergmann <[email protected]> > On Wed, May 15, 2019 at 9:36 AM Xiaowei Bao <[email protected]> wrote: > > Signed-off-by: Xiaowei Bao <[email protected]> > > --- > > arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 52 > > ++++++++++++++++++++++++ > > 1 files changed, 52 insertions(+), 0 deletions(-) > > > > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi > > b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi > > index b045812..50b579b 100644 > > --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi > > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi > > @@ -398,6 +398,58 @@ > > status = "disabled"; > > }; > > > > + pcie@3400000 { > > + compatible = "fsl,ls1028a-pcie"; > > + reg = <0x00 0x03400000 0x0 0x00100000 /* > > controller registers */ > > + 0x80 0x00000000 0x0 0x00002000>; /* > > configuration space */ > > + reg-names = "regs", "config"; > > + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* > > PME interrupt */ > > + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* > > aer interrupt */ > > + interrupt-names = "pme", "aer"; > > + #address-cells = <3>; > > + #size-cells = <2>; > > + device_type = "pci"; > > + dma-coherent; > > + num-lanes = <4>; > > + bus-range = <0x0 0xff>; > > + ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 > > 0x0 0x00010000 /* downstream I/O */ > > + 0x82000000 0x0 0x40000000 0x80 > > + 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ > > Are you sure there is no support for 64-bit BARs or prefetchable memory? > [Xiaowei Bao] sorry for late reply, Thought that our Layerscape platform has > not added prefetchable memory support in DTS, so this platform has not been > added, I will submit a separate patch to add prefetchable memory support for > all Layerscape platforms. Ok, thanks. > Of course, the prefetchable PCIE device can work in our boards, > because the RC will assign non-prefetchable memory for this device. We > reserve 1G no-prefetchable memory for PCIE device, it is enough for general > devices. Sure, many devices work just fine, this is mostly a question of supporting those devices that do require multiple gigabytes, or that need prefetchable memory semantics to get the expected performance. GPUs are the obvious example, but I think there are others (infiniband?). [Xiaowei Bao] sorry, I don't know much about infiniband and GPU, as you said, I think many devices works fine with this DTS, I will add the prefetchable memory entry in DTS future and submit another patch. Arnd
