On 10/05/2019 13:29, Amit Kucheria wrote:
> Add device bindings for cpuidle states for cpu devices.
> 
> Signed-off-by: Amit Kucheria <[email protected]>
> ---
>  arch/arm64/boot/dts/qcom/msm8996.dtsi | 28 +++++++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi 
> b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> index c761269caf80..b615bcb9e351 100644
> --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> @@ -95,6 +95,7 @@
>                       compatible = "qcom,kryo";
>                       reg = <0x0 0x0>;
>                       enable-method = "psci";
> +                     cpu-idle-states = <&LITTLE_CPU_PD>;

It is the same micro architecture, the CPUS differ by their max OPP.
Shall we call it really little?

I take the opportunity to report the capacity-dmips-mhz attribute is
missing. The max capacity computation is not triggered, thus the
scheduler see the same capacity for both cluster even if one has less
OPP. Adding capacity-dmips-mhz = <1024>; to all CPUs will fix it.

>                       next-level-cache = <&L2_0>;
>                       L2_0: l2-cache {
>                             compatible = "cache";
> @@ -107,6 +108,7 @@
>                       compatible = "qcom,kryo";
>                       reg = <0x0 0x1>;
>                       enable-method = "psci";
> +                     cpu-idle-states = <&LITTLE_CPU_PD>;
>                       next-level-cache = <&L2_0>;
>               };
>  
> @@ -115,6 +117,7 @@
>                       compatible = "qcom,kryo";
>                       reg = <0x0 0x100>;
>                       enable-method = "psci";
> +                     cpu-idle-states = <&BIG_CPU_PD>;
>                       next-level-cache = <&L2_1>;
>                       L2_1: l2-cache {
>                             compatible = "cache";
> @@ -127,6 +130,7 @@
>                       compatible = "qcom,kryo";
>                       reg = <0x0 0x101>;
>                       enable-method = "psci";
> +                     cpu-idle-states = <&BIG_CPU_PD>;
>                       next-level-cache = <&L2_1>;
>               };
>  
> @@ -151,6 +155,30 @@
>                               };
>                       };
>               };
> +
> +             idle-states {
> +                     entry-method="psci";
> +
> +                     LITTLE_CPU_PD: little-power-down {
> +                             compatible = "arm,idle-state";
> +                             idle-state-name = "standalone-power-collapse";
> +                             arm,psci-suspend-param = <0x00000004>;
> +                             entry-latency-us = <40>;
> +                             exit-latency-us = <40>;
> +                             min-residency-us = <300>;
> +                             local-timer-stop;
> +                     };
> +
> +                     BIG_CPU_PD: big-power-down {
> +                             compatible = "arm,idle-state";
> +                             idle-state-name = "standalone-power-collapse";
> +                             arm,psci-suspend-param = <0x00000004>;
> +                             entry-latency-us = <40>;
> +                             exit-latency-us = <40>;
> +                             min-residency-us = <300>;
> +                             local-timer-stop;
> +                     };
> +             };
>       };
>  
>       thermal-zones {
> 


-- 
 <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs

Follow Linaro:  <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog

Reply via email to