On Mon, 17 Dec 2018 01:37:58 PST (-0800), [email protected] wrote:
On Fri, Nov 30, 2018 at 1:32 PM Anup Patel <[email protected]> wrote:
This patchset primarily adds IRQ affinity support in PLIC driver and
other improvements.
The patchset gives mechanism for explicitly routing external interrupts to
particular CPUs using smp_affinity attribute of each Linux IRQs. Also, we
can now use IRQ balancer from kernel-space or user-space.
The patchset is tested on QEMU virt machine. It is based on Linux-4.20-rc4
and can be found at riscv_plic_irq_affinity_v3 branch of:
https://github.com/avpatel/linux.git
Changes since v2:
- Fixed incorrect address of enable registers using sizeof(u32) in PATCH1
- Retained comment about need for locking in PATCH1
- Split PATCH2 into two patches
- Split PATCH3 into two patches
- Minor fix in commit description of PATCH4
Changes since v1:
- Removed few whitspace changes from PATCH1
- Keep use of DEFINE_PER_CPU() as it is
Anup Patel (6):
irqchip: sifive-plic: Pre-compute context hart base and enable base
irqchip: sifive-plic: Add struct plic_hw for global PLIC HW details
irqchip: sifive-plic: More flexible plic_irq_toggle()
irqchip: sifive-plic: Add warning in plic_init() if handler already
present
irqchip: sifive-plic: Differentiate between PLIC handler and context
irqchip: sifive-plic: Implement irq_set_affinity() for SMP host
drivers/irqchip/irq-sifive-plic.c | 143 +++++++++++++++++++-----------
1 file changed, 90 insertions(+), 53 deletions(-)
--
2.17.1
Any comments on this series?
I also haven't had a chance to look at these yet.
