Hi Jonathan,
> -----Original Message----- > From: Jonathan Cameron [mailto:[email protected]] > Sent: Sunday, July 29, 2018 5:21 PM > To: Manish Narani <[email protected]> > Cc: Sai Krishna Potthuri <[email protected]>; Michal Simek > <[email protected]>; [email protected]; [email protected]; > [email protected]; Anirudha Sarangi <[email protected]>; Srinivas Goud > <[email protected]>; [email protected]; linux-arm- > [email protected]; [email protected] > Subject: Re: [PATCH v2 2/4] iio: adc: xilinx: limit pcap clock frequency value > > On Mon, 23 Jul 2018 20:32:01 +0530 > Manish Narani <[email protected]> wrote: > > > This patch limits the xadc pcap clock frequency value to be less than > > 200MHz. This fixes the issue when zynq is booted at higher frequency > > values, pcap crosses the maximum limit of 200MHz(Fmax) as it is > > derived from IOPLL. > > If this limit is crossed it is required to alter the WEDGE and REDGE > > bits of XADC_CFG register to make timings better in the interface. So > > to avoid alteration of these bits every time, the pcap value should > > not cross the Fmax limit. > > > > Signed-off-by: Manish Narani <[email protected]> > > Applied, to the togreg branch of iio.git. If you want this backported to > stable, > then request it once this patch is upstream. It may be sometime given we've > probably just missed the coming merge window. > > If you do need it faster then let me know and I'll look at moving it over to > the > branch of fixes during the RC phases. Thanks for getting this applied. There is no concern for this to be in the stable ASAP. I can wait. Thanks & Regards, Manish Narani
