From: Joerg Roedel <[email protected]> This is the last part of the PAE page-table setup for PAE before we can add the CR3 switch to the entry code.
Signed-off-by: Joerg Roedel <[email protected]> --- arch/x86/include/asm/pgtable-3level.h | 3 +++ arch/x86/mm/pti.c | 7 +++++++ 2 files changed, 10 insertions(+) diff --git a/arch/x86/include/asm/pgtable-3level.h b/arch/x86/include/asm/pgtable-3level.h index bc4af5453802..910f0b35370e 100644 --- a/arch/x86/include/asm/pgtable-3level.h +++ b/arch/x86/include/asm/pgtable-3level.h @@ -98,6 +98,9 @@ static inline void native_set_pmd(pmd_t *pmdp, pmd_t pmd) static inline void native_set_pud(pud_t *pudp, pud_t pud) { +#ifdef CONFIG_PAGE_TABLE_ISOLATION + pud.p4d.pgd = pti_set_user_pgd(&pudp->p4d.pgd, pud.p4d.pgd); +#endif set_64bit((unsigned long long *)(pudp), native_pud_val(pud)); } diff --git a/arch/x86/mm/pti.c b/arch/x86/mm/pti.c index 6b6bfd13350e..a561b5625d6c 100644 --- a/arch/x86/mm/pti.c +++ b/arch/x86/mm/pti.c @@ -122,6 +122,7 @@ pgd_t __pti_set_user_pgd(pgd_t *pgdp, pgd_t pgd) */ kernel_to_user_pgdp(pgdp)->pgd = pgd.pgd; +#ifdef CONFIG_X86_64 /* * If this is normal user memory, make it NX in the kernel * pagetables so that, if we somehow screw up and return to @@ -134,10 +135,16 @@ pgd_t __pti_set_user_pgd(pgd_t *pgdp, pgd_t pgd) * may execute from it * - we don't have NX support * - we're clearing the PGD (i.e. the new pgd is not present). + * - We run on a 32 bit kernel. 2-level paging doesn't support NX at + * all and PAE paging does not support it on the PGD level. We can + * set it in the PMD level there in the future, but that means we + * need to unshare the PMDs between the kernel and the user + * page-tables. */ if ((pgd.pgd & (_PAGE_USER|_PAGE_PRESENT)) == (_PAGE_USER|_PAGE_PRESENT) && (__supported_pte_mask & _PAGE_NX)) pgd.pgd |= _PAGE_NX; +#endif /* return the copy of the PGD we want the kernel to use: */ return pgd; -- 2.13.6
