On Thu, Nov 02, 2017 at 05:16:44PM +0000, Will Deacon wrote:
> On Thu, Nov 02, 2017 at 01:08:52PM -0400, Alan Stern wrote:
> > Right. To address your point: release + acquire isn't the same as a
> > full barrier either. The SB pattern illustrates the difference:
> >
> > P0 P1
> > Write x=1 Write y=1
> > Release a smp_mb
> > Acquire b Read x=0
> > Read y=0
> >
> > This would not be allowed if the release + acquire sequence was
> > replaced by smp_mb. But as it stands, this is allowed because nothing
> > prevents the CPU from interchanging the order of the release and the
> > acquire -- and then you're back to the acquire + release case.
> >
> > However, there is one circumstance where this interchange isn't
> > allowed: when the release and acquire access the same memory
> > location. Thus:
> >
> > P0(int *x, int *y, int *a)
> > {
> > int r0;
> >
> > WRITE_ONCE(*x, 1);
> > smp_store_release(a, 1);
> > smp_load_acquire(a);
> > r0 = READ_ONCE(*y);
> > }
> >
> > P1(int *x, int *y)
> > {
> > int r1;
> >
> > WRITE_ONCE(*y, 1);
> > smp_mb();
> > r1 = READ_ONCE(*x);
> > }
> >
> > exists (0:r0=0 /\ 1:r1=0)
> >
> > This is forbidden. It would remain forbidden even if the smp_mb in P1
> > were replaced by a similar release/acquire pair for the same memory
> > location.
>
> Isn't this allowed on x86 mapping smp_mb() to mfence, store-release to plain
> store and load-acquire to plain load? All we're saying is that you can forward
> from a release to an acquire, which is fine for RCpc semantics.
Yeah, as it happens I talked to Will about that exact case while writing
that email :-), this is why he has that thing handy.
