Hi Vlad,
On 21-04-2017 12:45, Vlad Zakharov wrote: > AXS10X boards manages it's clocks using various PLLs. These PLL has same > dividers and corresponding control registers mapped to different addresses. > So we add one common driver for such PLLs. > > Each PLL on AXS10X board consist of three dividers: IDIV, FBDIV and > ODIV. Output clock value is managed using these dividers. > > We add pre-defined tables with supported rate values and appropriate > configurations of IDIV, FBDIV and ODIV for each value. > > As of today we add support for PLLs that generate clock for the > following devices: > * ARC core on AXC CPU tiles. > * ARC PGU on ARC SDP Mainboard. > and more to come later. > > Acked-by: Rob Herring <[email protected]> > Signed-off-by: Vlad Zakharov <[email protected]> > Signed-off-by: Jose Abreu <[email protected]> > Cc: Michael Turquette <[email protected]> > Cc: Stephen Boyd <[email protected]> > Cc: Mark Rutland <[email protected]> > --- > Changes v2..v3 > - replaced complex data structures with simple cfg tables > - replaced non-hw based provider and clk registration functions with > hw-based > - fixed typos and minor code styling issues > > .../devicetree/bindings/clock/snps,pll-clock.txt | 28 ++ > MAINTAINERS | 6 + > drivers/clk/axs10x/Makefile | 1 + > drivers/clk/axs10x/pll_clock.c | 334 > +++++++++++++++++++++ > 4 files changed, 369 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/snps,pll-clock.txt > create mode 100644 drivers/clk/axs10x/pll_clock.c > [snip] > > +SYNOPSYS ARC SDP clock driver > +M: Vlad Zakharov <[email protected]> > +S: Supported > +F: drivers/clk/axs10x/* Acked-by: Jose Abreu <[email protected]> Best regards, Jose Miguel Abreu > +F: Documentation/devicetree/bindings/clock/snps,pll-clock.txt > + > SYSTEM CONFIGURATION (SYSCON) > M: Lee Jones <[email protected]> > M: Arnd Bergmann <[email protected]> >
