On 23/03/16 09:18, Alexander Stein wrote:
> On Monday 07 March 2016 11:36:22, Minghuan Lian wrote:
>> Some kind of NXP Layerscape SoC provides a MSI
>> implementation which uses two SCFG registers MSIIR and
>> MSIR to support 32 MSI interrupts for each PCIe controller.
>> The patch is to support it.
>>
>> Signed-off-by: Minghuan Lian <[email protected]>
>
> Tested-by: Alexander Stein <[email protected]>
>
> Using an intel e1000e card which uses 3 MSIs. But the IRQ numbers are a bit
> strange though:
>> grep eth3 /proc/interrupts
>>
>> 63: 49 0 MSI 134742016 Edge eth3-rx-0
>> 64: 3 0 MSI 134742017 Edge eth3-tx-0
>> 65: 4 0 MSI 134742018 Edge eth3
This is a virtual interrupt number (despite being displayed as a hwirq),
computed from the PCI requester ID and the MSI index. You shouldn't
infer anything from it.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
