Some Zhaoxin CPUs declare support SSE4.2 instruction sets but
having a CRC32C instruction implementation that not working as
intended. Set low performance CRC32C flag on these CPUs for later
use.
Signed-off-by: Tony W Wang-oc <tonywwang...@zhaoxin.com>
---
arch/x86/kernel/cpu/centaur.c | 7 +++++++
arch/x86/kernel/cpu/zhaoxin.c | 6 ++++++
2 files changed, 13 insertions(+)
diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index 345f7d9..13e6fbe 100644
--- a/arch/x86/kernel/cpu/centaur.c
+++ b/arch/x86/kernel/cpu/centaur.c
@@ -109,6 +109,13 @@ static void early_init_centaur(struct cpuinfo_x86 *c)
set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
}
+
+ /*
+ * These CPUs declare support SSE4.2 instruction sets but
+ * having low performance CRC32C instruction implementation.
+ */
+ if (c->x86 == 0x6 || (c->x86 == 0x7 && c->x86_model <= 0x3b))
+ set_cpu_cap(c, X86_FEATURE_CRC32C);
}
static void init_centaur(struct cpuinfo_x86 *c)
diff --git a/arch/x86/kernel/cpu/zhaoxin.c b/arch/x86/kernel/cpu/zhaoxin.c
index 05fa4ef..837ec65 100644
--- a/arch/x86/kernel/cpu/zhaoxin.c
+++ b/arch/x86/kernel/cpu/zhaoxin.c
@@ -79,6 +79,12 @@ static void early_init_zhaoxin(struct cpuinfo_x86 *c)
c->x86_coreid_bits = get_count_order((ebx >> 16) &
0xff);
}
+ /*
+ * These CPUs declare support SSE4.2 instruction sets but
+ * having low performance CRC32C instruction implementation.
+ */
+ if (c->x86 == 0x6 || (c->x86 == 0x7 && c->x86_model <= 0x3b))
+ set_cpu_cap(c, X86_FEATURE_CRC32C);
}
static void init_zhaoxin(struct cpuinfo_x86 *c)
--
2.7.4
