Re: [PATCH] crypto: x86/crc32c-intel - Don't match some Zhaoxin CPUs

[Peter Zijlstra]

On Mon, Dec 14, 2020 at 11:59:52AM +0800, Tony W Wang-oc wrote:

Didn't I mention something about a comment?

>  static const struct x86_cpu_id crc32c_cpu_id[] = {
> +     X86_MATCH_VENDOR_FAM_FEATURE(ZHAOXIN, 0x6, X86_FEATURE_XMM4_2, 1),
> +     X86_MATCH_VENDOR_FAM_MODEL_FEATURE(ZHAOXIN, 0x7, 0x1b, 
> X86_FEATURE_XMM4_2, 1),
> +     X86_MATCH_VENDOR_FAM_MODEL_FEATURE(ZHAOXIN, 0x7, 0x3b, 
> X86_FEATURE_XMM4_2, 1),
> +     X86_MATCH_VENDOR_FAM_FEATURE(CENTAUR, 0x6, X86_FEATURE_XMM4_2, 1),
> +     X86_MATCH_VENDOR_FAM_MODEL_FEATURE(CENTAUR, 0x7, 0x1b, 
> X86_FEATURE_XMM4_2, 1),
> +     X86_MATCH_VENDOR_FAM_MODEL_FEATURE(CENTAUR, 0x7, 0x3b, 
> X86_FEATURE_XMM4_2, 1),
>       X86_MATCH_FEATURE(X86_FEATURE_XMM4_2, NULL),
>       {}

Also, the above is weird in that is has the negative entries marked
positive, and 1/NULL are inconsistent.

Something like so then?

---

diff --git a/arch/x86/crypto/crc32c-intel_glue.c 
b/arch/x86/crypto/crc32c-intel_glue.c
index feccb5254c7e..f6e6669a5102 100644
--- a/arch/x86/crypto/crc32c-intel_glue.c
+++ b/arch/x86/crypto/crc32c-intel_glue.c
@@ -215,14 +215,31 @@ static struct shash_alg alg = {
 };
 
 static const struct x86_cpu_id crc32c_cpu_id[] = {
-       X86_MATCH_FEATURE(X86_FEATURE_XMM4_2, NULL),
+       /*
+        * Negative entries; exclude these chips from using this driver.
+        * They match the positive rule below, but their CRC32 instruction
+        * implementation is so slow, it doesn't merrit use.
+        */
+       X86_MATCH_VENDOR_FAM_FEATURE(ZHAOXIN, 0x6, X86_FEATURE_XMM4_2, false),
+       X86_MATCH_VENDOR_FAM_MODEL_FEATURE(ZHAOXIN, 0x7, 0x1b, 
X86_FEATURE_XMM4_2, false),
+       X86_MATCH_VENDOR_FAM_MODEL_FEATURE(ZHAOXIN, 0x7, 0x3b, 
X86_FEATURE_XMM4_2, false),
+       X86_MATCH_VENDOR_FAM_FEATURE(CENTAUR, 0x6, X86_FEATURE_XMM4_2, false),
+       X86_MATCH_VENDOR_FAM_MODEL_FEATURE(CENTAUR, 0x7, 0x1b, 
X86_FEATURE_XMM4_2, false),
+       X86_MATCH_VENDOR_FAM_MODEL_FEATURE(CENTAUR, 0x7, 0x3b, 
X86_FEATURE_XMM4_2, false),
+       /*
+        * Positive entry; SSE-4.2 instructions include special purpose CRC32
+        * instructions.
+        */
+       X86_MATCH_FEATURE(X86_FEATURE_XMM4_2, true),
        {}
 };
 MODULE_DEVICE_TABLE(x86cpu, crc32c_cpu_id);
 
 static int __init crc32c_intel_mod_init(void)
 {
-       if (!x86_match_cpu(crc32c_cpu_id))
+       const struct x86_cpu_id *m = x86_match_cpu(crc32c_cpu_id);
+
+       if (!m || !m->driver_data)
                return -ENODEV;
 #ifdef CONFIG_X86_64
        if (boot_cpu_has(X86_FEATURE_PCLMULQDQ)) {