From: Keerthy <j-keer...@ti.com>
Add crypto accelarator node for supporting hardware crypto algorithms,
including SHA1, SHA256, SHA512, AES, 3DES, and AEAD suites.
Signed-off-by: Keerthy <j-keer...@ti.com>
[t-kri...@ti.com: Modifications based on introduction of yaml binding]
Signed-off-by: Tero Kristo <t-kri...@ti.com>
---
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index 61815228e230..4615f2009a35 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -112,6 +112,28 @@
power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
};
+ crypto: crypto@4E00000 {
+ compatible = "ti,am654-sa2ul";
+ reg = <0x0 0x4E00000 0x0 0x1200>;
+ power-domains = <&k3_pds 136 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x04E00000 0x00 0x04E00000 0x0 0x30000>;
+ status = "okay";
+
+ dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
+ <&main_udmap 0x4001>;
+ dma-names = "tx", "rx1", "rx2";
+ dma-coherent;
+
+ rng: rng@4e10000 {
+ compatible = "inside-secure,safexcel-eip76";
+ reg = <0x0 0x4e10000 0x0 0x7d>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&k3_clks 136 1>;
+ };
+ };
+
main_pmx0: pinmux@11c000 {
compatible = "pinctrl-single";
reg = <0x0 0x11c000 0x0 0x2e4>;
--
2.17.1
--
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