On Wed, 2018-06-13 at 07:32:40 UTC, Haren Myneni wrote: > NX increments readOffset by FIFO size in receive FIFO control register > when CRB is read. But the index in RxFIFO has to match with the > corresponding entry in FIFO maintained by VAS in kernel. Otherwise NX > may be processing incorrect CRBs and can cause CRB timeout. > > VAS FIFO offset is 0 when the receive window is opened during > initialization. When the module is reloaded or in kexec boot, readOffset > in FIFO control register may not match with VAS entry. This patch adds > nx_coproc_init OPAL call to reset readOffset and queued entries in FIFO > control register for both high and normal FIFOs. > > Signed-off-by: Haren Myneni <ha...@us.ibm.com>
Applied to powerpc next, thanks. https://git.kernel.org/powerpc/c/656ecc16e8fc2ab44b3d70e3fcc197 cheers
