On Mon, Sep 24, 2018 at 02:48:16PM +0200, Ard Biesheuvel wrote:
> For historical reasons, the AES-NI based implementation of the PCBC
> chaining mode uses a special FPU chaining mode wrapper template to
> amortize the FPU start/stop overhead over multiple blocks.
> 
> When this FPU wrapper was introduced, it supported widely used
> chaining modes such as XTS and CTR (as well as LRW), but currently,
> PCBC is the only remaining user.
> 
> Since there are no known users of pcbc(aes) in the kernel, let's remove
> this special driver, and rely on the generic pcbc driver to encapsulate
> the AES-NI core cipher.
> 
> Signed-off-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
> ---
>  arch/x86/crypto/Makefile           |   2 +-
>  arch/x86/crypto/aesni-intel_glue.c |  32 ---
>  arch/x86/crypto/fpu.c              | 207 --------------------
>  crypto/Kconfig                     |   2 +-
>  4 files changed, 2 insertions(+), 241 deletions(-)

Patch applied.  Thanks.
-- 
Email: Herbert Xu <herb...@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt

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