Modify the Scatter-Gather entry definitions for the Freescale
CAAM driver to include support for both 64- and 32-bit DMA pointers.

Signed-off-by: Victoria Milhoan <vicki.milh...@freescale.com>
---
 drivers/crypto/caam/desc.h       | 25 +++++++++++++++++++++----
 drivers/crypto/caam/sg_sw_sec4.h |  1 -
 2 files changed, 21 insertions(+), 5 deletions(-)

diff --git a/drivers/crypto/caam/desc.h b/drivers/crypto/caam/desc.h
index d397ff9..405acbf 100644
--- a/drivers/crypto/caam/desc.h
+++ b/drivers/crypto/caam/desc.h
@@ -8,12 +8,29 @@
 #ifndef DESC_H
 #define DESC_H
 
+/*
+ * 16-byte hardware scatter/gather table
+ * An 8-byte table exists in the hardware spec, but has never been
+ * implemented to date. The 8/16 option is selected at RTL-compile-time.
+ * and this selection is visible in the Compile Time Parameters Register
+ */
+
+#define SEC4_SG_LEN_EXT                0x80000000      /* Entry points to 
table */
+#define SEC4_SG_LEN_FIN                0x40000000      /* Last ent in table */
+#define SEC4_SG_BPID_MASK      0x000000ff
+#define SEC4_SG_BPID_SHIFT     16
+#define SEC4_SG_LEN_MASK       0x3fffffff      /* Excludes EXT and FINAL */
+#define SEC4_SG_OFFS_MASK      0x00001fff
+
 struct sec4_sg_entry {
-       u64 ptr;
-#define SEC4_SG_LEN_FIN 0x40000000
-#define SEC4_SG_LEN_EXT 0x80000000
+#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
+       dma_addr_t ptr;
+#else
+       u32 rsvd1;
+       dma_addr_t ptr;
+#endif
        u32 len;
-       u8 reserved;
+       u8 rsvd2;
        u8 buf_pool_id;
        u16 offset;
 };
diff --git a/drivers/crypto/caam/sg_sw_sec4.h b/drivers/crypto/caam/sg_sw_sec4.h
index b68b74c..711bb39 100644
--- a/drivers/crypto/caam/sg_sw_sec4.h
+++ b/drivers/crypto/caam/sg_sw_sec4.h
@@ -15,7 +15,6 @@ static inline void dma_to_sec4_sg_one(struct sec4_sg_entry 
*sec4_sg_ptr,
 {
        sec4_sg_ptr->ptr = dma;
        sec4_sg_ptr->len = len;
-       sec4_sg_ptr->reserved = 0;
        sec4_sg_ptr->buf_pool_id = 0;
        sec4_sg_ptr->offset = offset;
 #ifdef DEBUG
-- 
2.1.4

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