On Mon, Jun 23, 2014 at 03:08:28PM +0530, Ruchika Gupta wrote: > Some registers like SECVID, CHAVID, CHA Revision Number, > CTPR were defined as 64 bit resgisters. The IP provides > a DWT bit(Double word Transpose) to transpose the two words when > a double word register is accessed. However setting this bit > would also affect the operation of job descriptors as well as > other registers which are truly double word in nature. > So, for the IP to work correctly on big-endian as well as > little-endian SoC's, change is required to access all 32 bit > registers as 32 bit quantities. > > Signed-off-by: Ruchika Gupta <ruchika.gu...@freescale.com>
Patch applied. -- Email: Herbert Xu <herb...@gondor.apana.org.au> Home Page: http://gondor.apana.org.au/~herbert/ PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt -- To unsubscribe from this list: send the line "unsubscribe linux-crypto" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
