Progress:
* UM-2 [QEMU upstream maintainership]
- patch review:
+ v4 of the raspi-4 SoC/board model series (this is a big one)
+ bug in calculation of limit address in designware pci controller model
+ imx7 serial device: implementation of FIFO and ageing timer
+ patchset to reduce size of fdt blob
- started looking at some of my old device/bus reset cleanup patches,
since another dev on-list was running into a potential issue that
they might help to solve. Failed to repro the test failure that was
the reason I put them on the back burner, so sent them out to the
list as-is...
* QEMU-598 [Model the MPS3-AN536 dual-Cortex-R52 FPGA image]
- updated the SCC device to handle the AN536 specifics (most
actual behaviour will be unimplemented, as we do for our other
board models that have this device)
- checked that we don't need to make any changes to the ioregs
device; the existing model is flexible enough we can configure
it to match the AN536 specifics
- wrote the initial skeleton of the board model (which only creates
the RAM and ROM regions for the moment)
- realized that it might be better to wait for Philippe's reworking
of hw/cpu/a15mpcore.c and friends before adding another similar
object for the Cortex-R52
thanks
-- PMM
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