Successfully identified regression in *llvm* in CI configuration
tcwg_bmk_llvm_tx1/llvm-master-aarch64-spec2k6-O2. So far, this commit has
regressed CI configurations:
- tcwg_bmk_llvm_tx1/llvm-master-aarch64-spec2k6-O2
Culprit:
<cut>
commit 2f69b78a578dad55f0fde3c184a3dc0ea615fd43
Author: Florian Hahn <f...@fhahn.com>
Date: Sun May 16 11:12:55 2021 +0100
[VectorCombine] Add tests with and & urem guaranteeing idx is valid.
</cut>
Results regressed to (for first_bad == 2f69b78a578dad55f0fde3c184a3dc0ea615fd43)
# reset_artifacts:
-10
# build_abe binutils:
-9
# build_abe stage1 -- --set gcc_override_configure=--disable-libsanitizer:
-8
# build_abe linux:
-7
# build_abe glibc:
-6
# build_abe stage2 -- --set gcc_override_configure=--disable-libsanitizer:
-5
# build_llvm true:
-3
# true:
0
# benchmark -O2 --
artifacts/build-2f69b78a578dad55f0fde3c184a3dc0ea615fd43/results_id:
1
# 447.dealII,dealII_base.default regressed by 103
# 447.dealII,[.] _ZN16ConstraintMatrix8add_lineEj regressed by 113
from (for last_good == a39f85d118cc4c7045e710302115da034bb3cb22)
# reset_artifacts:
-10
# build_abe binutils:
-9
# build_abe stage1 -- --set gcc_override_configure=--disable-libsanitizer:
-8
# build_abe linux:
-7
# build_abe glibc:
-6
# build_abe stage2 -- --set gcc_override_configure=--disable-libsanitizer:
-5
# build_llvm true:
-3
# true:
0
# benchmark -O2 --
artifacts/build-a39f85d118cc4c7045e710302115da034bb3cb22/results_id:
1
Artifacts of last_good build:
https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-aarch64-spec2k6-O2/9/artifact/artifacts/build-a39f85d118cc4c7045e710302115da034bb3cb22/
Results ID of last_good:
tx1_64/tcwg_bmk_llvm_tx1/bisect-llvm-master-aarch64-spec2k6-O2/1645
Artifacts of first_bad build:
https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-aarch64-spec2k6-O2/9/artifact/artifacts/build-2f69b78a578dad55f0fde3c184a3dc0ea615fd43/
Results ID of first_bad:
tx1_64/tcwg_bmk_llvm_tx1/bisect-llvm-master-aarch64-spec2k6-O2/1644
Build top page/logs:
https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-aarch64-spec2k6-O2/9/
Configuration details:
Reproduce builds:
<cut>
mkdir investigate-llvm-2f69b78a578dad55f0fde3c184a3dc0ea615fd43
cd investigate-llvm-2f69b78a578dad55f0fde3c184a3dc0ea615fd43
git clone https://git.linaro.org/toolchain/jenkins-scripts
mkdir -p artifacts/manifests
curl -o artifacts/manifests/build-baseline.sh
https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-aarch64-spec2k6-O2/9/artifact/artifacts/manifests/build-baseline.sh
--fail
curl -o artifacts/manifests/build-parameters.sh
https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-aarch64-spec2k6-O2/9/artifact/artifacts/manifests/build-parameters.sh
--fail
curl -o artifacts/test.sh
https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-aarch64-spec2k6-O2/9/artifact/artifacts/test.sh
--fail
chmod +x artifacts/test.sh
# Reproduce the baseline build (build all pre-requisites)
./jenkins-scripts/tcwg_bmk-build.sh @@ artifacts/manifests/build-baseline.sh
# Save baseline build state (which is then restored in artifacts/test.sh)
rsync -a --del --delete-excluded --exclude bisect/ --exclude artifacts/
--exclude llvm/ ./ ./bisect/baseline/
cd llvm
# Reproduce first_bad build
git checkout --detach 2f69b78a578dad55f0fde3c184a3dc0ea615fd43
../artifacts/test.sh
# Reproduce last_good build
git checkout --detach a39f85d118cc4c7045e710302115da034bb3cb22
../artifacts/test.sh
cd ..
</cut>
History of pending regressions and results:
https://git.linaro.org/toolchain/ci/base-artifacts.git/log/?h=linaro-local/ci/tcwg_bmk_llvm_tx1/llvm-master-aarch64-spec2k6-O2
Artifacts:
https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-aarch64-spec2k6-O2/9/artifact/artifacts/
Build log:
https://ci.linaro.org/job/tcwg_bmk_ci_llvm-bisect-tcwg_bmk_tx1-llvm-master-aarch64-spec2k6-O2/9/consoleText
Full commit (up to 1000 lines):
<cut>
commit 2f69b78a578dad55f0fde3c184a3dc0ea615fd43
Author: Florian Hahn <f...@fhahn.com>
Date: Sun May 16 11:12:55 2021 +0100
[VectorCombine] Add tests with and & urem guaranteeing idx is valid.
---
.../AArch64/load-extractelement-scalarization.ll | 60 +++++++++++++++++++
.../Transforms/VectorCombine/load-insert-store.ll | 68 ++++++++++++++++++++++
2 files changed, 128 insertions(+)
diff --git
a/llvm/test/Transforms/VectorCombine/AArch64/load-extractelement-scalarization.ll
b/llvm/test/Transforms/VectorCombine/AArch64/load-extractelement-scalarization.ll
index 3f8e276f06ca..5e105031ec78 100644
---
a/llvm/test/Transforms/VectorCombine/AArch64/load-extractelement-scalarization.ll
+++
b/llvm/test/Transforms/VectorCombine/AArch64/load-extractelement-scalarization.ll
@@ -113,6 +113,66 @@ entry:
declare void @llvm.assume(i1)
+define i32 @load_extract_idx_var_i64_known_valid_by_and(<4 x i32>* %x, i64
%idx) {
+; CHECK-LABEL: @load_extract_idx_var_i64_known_valid_by_and(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[IDX_CLAMPED:%.*]] = and i64 [[IDX:%.*]], 3
+; CHECK-NEXT: [[LV:%.*]] = load <4 x i32>, <4 x i32>* [[X:%.*]], align 16
+; CHECK-NEXT: [[R:%.*]] = extractelement <4 x i32> [[LV]], i64
[[IDX_CLAMPED]]
+; CHECK-NEXT: ret i32 [[R]]
+;
+entry:
+ %idx.clamped = and i64 %idx, 3
+ %lv = load <4 x i32>, <4 x i32>* %x
+ %r = extractelement <4 x i32> %lv, i64 %idx.clamped
+ ret i32 %r
+}
+
+define i32 @load_extract_idx_var_i64_not_known_valid_by_and(<4 x i32>* %x, i64
%idx) {
+; CHECK-LABEL: @load_extract_idx_var_i64_not_known_valid_by_and(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[IDX_CLAMPED:%.*]] = and i64 [[IDX:%.*]], 4
+; CHECK-NEXT: [[LV:%.*]] = load <4 x i32>, <4 x i32>* [[X:%.*]], align 16
+; CHECK-NEXT: [[R:%.*]] = extractelement <4 x i32> [[LV]], i64
[[IDX_CLAMPED]]
+; CHECK-NEXT: ret i32 [[R]]
+;
+entry:
+ %idx.clamped = and i64 %idx, 4
+ %lv = load <4 x i32>, <4 x i32>* %x
+ %r = extractelement <4 x i32> %lv, i64 %idx.clamped
+ ret i32 %r
+}
+
+define i32 @load_extract_idx_var_i64_known_valid_by_urem(<4 x i32>* %x, i64
%idx) {
+; CHECK-LABEL: @load_extract_idx_var_i64_known_valid_by_urem(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[IDX_CLAMPED:%.*]] = urem i64 [[IDX:%.*]], 4
+; CHECK-NEXT: [[LV:%.*]] = load <4 x i32>, <4 x i32>* [[X:%.*]], align 16
+; CHECK-NEXT: [[R:%.*]] = extractelement <4 x i32> [[LV]], i64
[[IDX_CLAMPED]]
+; CHECK-NEXT: ret i32 [[R]]
+;
+entry:
+ %idx.clamped = urem i64 %idx, 4
+ %lv = load <4 x i32>, <4 x i32>* %x
+ %r = extractelement <4 x i32> %lv, i64 %idx.clamped
+ ret i32 %r
+}
+
+define i32 @load_extract_idx_var_i64_not_known_valid_by_urem(<4 x i32>* %x,
i64 %idx) {
+; CHECK-LABEL: @load_extract_idx_var_i64_not_known_valid_by_urem(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[IDX_CLAMPED:%.*]] = urem i64 [[IDX:%.*]], 5
+; CHECK-NEXT: [[LV:%.*]] = load <4 x i32>, <4 x i32>* [[X:%.*]], align 16
+; CHECK-NEXT: [[R:%.*]] = extractelement <4 x i32> [[LV]], i64
[[IDX_CLAMPED]]
+; CHECK-NEXT: ret i32 [[R]]
+;
+entry:
+ %idx.clamped = urem i64 %idx, 5
+ %lv = load <4 x i32>, <4 x i32>* %x
+ %r = extractelement <4 x i32> %lv, i64 %idx.clamped
+ ret i32 %r
+}
+
define i32 @load_extract_idx_var_i32(<4 x i32>* %x, i32 %idx) {
; CHECK-LABEL: @load_extract_idx_var_i32(
; CHECK-NEXT: [[LV:%.*]] = load <4 x i32>, <4 x i32>* [[X:%.*]], align 16
diff --git a/llvm/test/Transforms/VectorCombine/load-insert-store.ll
b/llvm/test/Transforms/VectorCombine/load-insert-store.ll
index e565bda0a08f..611d66978019 100644
--- a/llvm/test/Transforms/VectorCombine/load-insert-store.ll
+++ b/llvm/test/Transforms/VectorCombine/load-insert-store.ll
@@ -188,6 +188,74 @@ entry:
declare void @llvm.assume(i1)
+define void @insert_store_nonconst_index_known_valid_by_and(<16 x i8>* %q, i8
zeroext %s, i32 %idx) {
+; CHECK-LABEL: @insert_store_nonconst_index_known_valid_by_and(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[Q:%.*]], align 16
+; CHECK-NEXT: [[IDX_CLAMPED:%.*]] = and i32 [[IDX:%.*]], 7
+; CHECK-NEXT: [[VECINS:%.*]] = insertelement <16 x i8> [[TMP0]], i8
[[S:%.*]], i32 [[IDX_CLAMPED]]
+; CHECK-NEXT: store <16 x i8> [[VECINS]], <16 x i8>* [[Q]], align 16
+; CHECK-NEXT: ret void
+;
+entry:
+ %0 = load <16 x i8>, <16 x i8>* %q
+ %idx.clamped = and i32 %idx, 7
+ %vecins = insertelement <16 x i8> %0, i8 %s, i32 %idx.clamped
+ store <16 x i8> %vecins, <16 x i8>* %q
+ ret void
+}
+
+define void @insert_store_nonconst_index_not_known_valid_by_and(<16 x i8>* %q,
i8 zeroext %s, i32 %idx) {
+; CHECK-LABEL: @insert_store_nonconst_index_not_known_valid_by_and(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[Q:%.*]], align 16
+; CHECK-NEXT: [[IDX_CLAMPED:%.*]] = and i32 [[IDX:%.*]], 16
+; CHECK-NEXT: [[VECINS:%.*]] = insertelement <16 x i8> [[TMP0]], i8
[[S:%.*]], i32 [[IDX_CLAMPED]]
+; CHECK-NEXT: store <16 x i8> [[VECINS]], <16 x i8>* [[Q]], align 16
+; CHECK-NEXT: ret void
+;
+entry:
+ %0 = load <16 x i8>, <16 x i8>* %q
+ %idx.clamped = and i32 %idx, 16
+ %vecins = insertelement <16 x i8> %0, i8 %s, i32 %idx.clamped
+ store <16 x i8> %vecins, <16 x i8>* %q
+ ret void
+}
+
+define void @insert_store_nonconst_index_known_valid_by_urem(<16 x i8>* %q, i8
zeroext %s, i32 %idx) {
+; CHECK-LABEL: @insert_store_nonconst_index_known_valid_by_urem(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[Q:%.*]], align 16
+; CHECK-NEXT: [[IDX_CLAMPED:%.*]] = urem i32 [[IDX:%.*]], 16
+; CHECK-NEXT: [[VECINS:%.*]] = insertelement <16 x i8> [[TMP0]], i8
[[S:%.*]], i32 [[IDX_CLAMPED]]
+; CHECK-NEXT: store <16 x i8> [[VECINS]], <16 x i8>* [[Q]], align 16
+; CHECK-NEXT: ret void
+;
+entry:
+ %0 = load <16 x i8>, <16 x i8>* %q
+ %idx.clamped = urem i32 %idx, 16
+ %vecins = insertelement <16 x i8> %0, i8 %s, i32 %idx.clamped
+ store <16 x i8> %vecins, <16 x i8>* %q
+ ret void
+}
+
+define void @insert_store_nonconst_index_not_known_valid_by_urem(<16 x i8>*
%q, i8 zeroext %s, i32 %idx) {
+; CHECK-LABEL: @insert_store_nonconst_index_not_known_valid_by_urem(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, <16 x i8>* [[Q:%.*]], align 16
+; CHECK-NEXT: [[IDX_CLAMPED:%.*]] = urem i32 [[IDX:%.*]], 17
+; CHECK-NEXT: [[VECINS:%.*]] = insertelement <16 x i8> [[TMP0]], i8
[[S:%.*]], i32 [[IDX_CLAMPED]]
+; CHECK-NEXT: store <16 x i8> [[VECINS]], <16 x i8>* [[Q]], align 16
+; CHECK-NEXT: ret void
+;
+entry:
+ %0 = load <16 x i8>, <16 x i8>* %q
+ %idx.clamped = urem i32 %idx, 17
+ %vecins = insertelement <16 x i8> %0, i8 %s, i32 %idx.clamped
+ store <16 x i8> %vecins, <16 x i8>* %q
+ ret void
+}
+
define void @insert_store_ptr_strip(<16 x i8>* %q, i8 zeroext %s) {
; CHECK-LABEL: @insert_store_ptr_strip(
; CHECK-NEXT: entry:
</cut>
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