On Wed, Mar 30, 2016 at 5:18 PM, yfw <fengwei....@linaro.org> wrote: > /tmp/ccZ40ViQ.s:1752: Error: selected processor does not support ARM mode > `cbnz r6,.L91'
Looking at gcc, I see that in thumb2 mode, for a conditional branch, it will emit cbnz if the target is in range and it is using a thumb2 low register, otherwise it emits cmp/bne. So this perhaps could be a bug with the compiler calculating instruction sizes wrong, and hence getting the range calculation from the branch to the target label wrong. We would need a reproducible testcase to investigate. The easiest way to do this if to add --save-temps to the g++ command, and then send us the UnwindCurrent.ii file. We also need the g++ command line, but you already gave us that. Otherwise, we have to figure out how to build AOSP with gcc-5.3. I'm not sure if anyone on the toolchain team is doing that regularly. There could also be something else going wrong here, e.g. the code could have extended asms using cbnz which aren't valid in thumb2 mode, the assembler could be somehow in thumb1 mode, etc, but these seem less likely in this case. Jim _______________________________________________ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
