Benchmark automation - TCWG-360 [5/10] * Flushed the rest of the easy stuff from my 'small fixups' to my 'staging' branch * Started rolling generic patches from my backport-benchmark branch into gerrit * Prodded at the prototype backport-benchmark job until the pieces worked ** Ran out of time to try an end-to-end run * Thought a little about permissions for access to source/results * Use of nc.traditional appears to have introduced a race condition
catomics - TCWG-436 [2/10] * Tried a run on A15 - same story as A57, good improvement on g8 libc ubenchmark that doesn't translate into SPEC subset * Performance counting the ubenchmark suggests variation around cache accesses on the catomic vs not-catomic code, didn't have any time to think about what, if anything, this means Misc [3/10] * Featuring an unusual level of ARM interruption * Especially concerns about change from multiarch to non-multiarch sysroot in binary releases =Plan= Confirm backport benchmarking working, roll remaining generic patches into gerrit Investigate the nc.traditional race Add a retry loop around LAVA boot (occasionally see LAVA-fail here) Create unit tests Follow up on (non-)multiarch sysroot issue _______________________________________________ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
