== GDB == * Committed follow-on patch to fix cosmetic issues resulting from the remote "info proc" patch set.
== GCC == * Created 4.6 backport branch including Richard's subreg forward- propagation branch, the modes-tieable patch, and the combine.c regression fix, and evaluated for correctness and performance. Investigation of performance regressions uncovered a problem in the register allocator: tied subregs (validly) cause somewhat larger register pressure in certain cases, and this caused the 4.6 IRA to generate spills. Note that the 4.7 IRA is still able to allocate every pseudo in the very same code; this is a result of Vladmir's significant IRA rewrite in 4.7 ... * Investigated Ramana's vld1 patches, and a problem with excessive vmov's in the PR 51819 test case pointed out by Ramana. It turns out that when we extract a lane from a vector to memory using an offsetted address, we move the value through a core register instead of simply computing the address and using vst1. I'm working on a patch to address this. Mit freundlichen Gruessen / Best Regards Ulrich Weigand -- Dr. Ulrich Weigand | Phone: +49-7031/16-3727 STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E. IBM Deutschland Research & Development GmbH Vorsitzender des Aufsichtsrats: Martin Jetter | Geschäftsführung: Dirk Wittkopp Sitz der Gesellschaft: Böblingen | Registergericht: Amtsgericht Stuttgart, HRB 243294 _______________________________________________ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-toolchain
