== This week == * Got the -fsched-pressure code into a state where it's almost presentable. Found a few more things to tweak on the way. Fixed some FIXMEs, notably to honour MAX_SCHED_READY_INSNS.
* More testing on ARM. Tried to get some SPEC2000 results as well as the usual EEMBC & DENbench, but I'm not sure how noisy the SPEC ones are. * More testing on powerpc. Decided that this really isn't a good target to test on for 4.7 because of the poor choice of pressure classes. SPEC CPU2006 INT results are reasonable-to-good, but the FP ones suffer from the fact that we think there are twice as many registers available for normal FP than there actually are. I'd like to fix this, but all pressure-estimation bits of GCC suffer from the same problem, and it's hard to justify as part of Linaro, because it doesn't apply to ARM. * Fixed upstream PR 50873 (ICE for NEON misaligned moves). Thanks to Ramana for the heads-up and analysis. * Retested and posted the patch for PR 48941 upstream (poor code generated by the vzip*() and vunzp*() arm_neon.h functions). Richard _______________________________________________ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-toolchain
