== Last week == * PR46934: Thumb-1 ICE, small fix in the "casesi" jump-table expand code. Quickly approved and committed upstream.
* Enhance XOR patch for gcc/simplify-rtx.c. Updated comments and committed upstream. * PR48250 / CS Issue #9845 / Launchpad #723185. Unaligned DImode reload under NEON. Submitted patch upstream, but still need to do some more verification that older pre-ARMv5TE cases are safe. Should complete this week. * Working on a type of ICE seen currently on upstream trunk, a few testcases failing under '-O3 -g'. It seems VTA related, but also might have something to do with register elimination not fully done for (var_location (entry_value ...)) expressions, leaving [afp+#num] memory addresses existing in debug insns after reload. Still investigating. * Launchpad #689887, ICE in get_arm_condition_code(). Pushed a merge request to Linaro 4.5 for this patch. Also another LP#742961 appeared as another case of this ICE... * Still working on (what I think should be) the last of the CoreMark ARMv6 regressions. The problem is to combine uxtb+cmp into ands #255. This could be done by adding (set (cc) (compare (zero_extend...))) patterns, implemented by ands assembly, but still looking if this can be done (probably more elegantly) by something like CANONICALIZE_COMPARISON (replacing compare operands) in the ARM backend. * Launchpad #736007, ICE immed_double_const under -mfpu=neon -g. Some discussion on gcc-patches about this, still unclear on what should be done... == This week == * Push forward on above issues. _______________________________________________ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-toolchain
