On Mon, 2011-01-31 at 16:02 +0200, Ira Rosen wrote:
> Hi,
> 
> I am trying to implement interleave_high/low and extract_even/odd
> using vzip and vuzp instructions. I am attaching a patch that attempts
> to do that. It uses already existing neon_vzip<mode>_internal. The
> problem with it is that it doesn't express the fact that the two
> outputs of vzip depend on both inputs, which causes wrong code
> generation in CSE:
> for
> (a,b)<- vzip (c,d)
> and
> (e,f) <- vzip (g,d)
> CSE decides that b==f, since on RTL level b and f depend only on d.
> 
> Here is neon_vzip<mode>_internal:
> 
> (define_insn "neon_vzip<mode>_internal"
>   [(set (match_operand:VDQW 0 "s_register_operand" "=w")
>        (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0")]
>                     UNSPEC_VZIP1))
>    (set (match_operand:VDQW 2 "s_register_operand" "=w")
>         (unspec:VDQW [(match_operand:VDQW 3 "s_register_operand" "2")]
>                     UNSPEC_VZIP2))]

Just to let you know, here, when I tried to make the two sets parallel
and "+w" for operands 0 and 2 (instead of =w), it made reload ICE. I did
this to represent the 'meaning' of the instruction in md-speak, but no
success :-(

Tejas.


>   "TARGET_NEON"
>   "vzip.<V_sz_elem>\t%<V_reg>0, %<V_reg>2"
>   [(set (attr "neon_type")
>       (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
>                     (const_string "neon_bp_simple")
>                     (const_string "neon_bp_3cycle")))]
> )
> 
> Is there a way to properly mark the dependence?
> 
> Thanks,
> Ira
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> linaro-toolchain@lists.linaro.org 
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