Hi Ramana,

On 16 December 2010 20:11, Ramana Radhakrishnan
<ramana.radhakrish...@arm.com> wrote:
> Hi Ira,
>
> On Thu, 2010-12-16 at 15:29 +0200, Ira Rosen wrote:
>> - telecom viterbi (vectorization potential gain is 4x) requires
>> conditional store sinking and load hoisting to enable if-conversion. I
>> worked on implementation of store sinking this week.
>
> Is this the only feature that viterbi needs for vectorization ?
>
> >From some research that Tejas did earlier this year, I thought that
> viterbi was among the hardest to vectorize because in addition to what
> you mention we need to support vld/st2 or (ofcourse vzip and vld1 if we
> don't support vld2) instructions and the other vbif / vbsl instructions
> to support vectorization for viterbi.

Right, we need vld2 and vst2 for Viterbi, and we are working on their
implementation (see this thread for the latest discussion
http://lists.linaro.org/pipermail/linaro-toolchain/2010-December/000540.html).

>
> I see that we support v<cond> in the backend now but we don't support
> the vector bitfield instructions like vbit / vbif and vbsl which can be
> used for vector select other than through intrinsics.

I haven't checked this. But in any case vector select is very
important and it's a good idea to support it anyway.

Ira

>
> I could be of-course missing something here ....
>
> cheers
> Ramana
>
>
>
>>
>> Ira
>>
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>
>
>

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