EOT message on GEN9 has used R112-R127, but the same message on GEN7-GEN8 still uses other registers. To avoid potential issues, use R112-R127 on GEN7-GEN8 too
In additition, GEN7-GEN9 use the same 'write' message, so factor out the same code to exa_wm_write.g7i in this patch Signed-off-by: Xiang, Haihao <[email protected]> --- src/shaders/render/Makefile.am | 3 +- src/shaders/render/exa_wm_write.g7a | 59 +-------------------------- src/shaders/render/exa_wm_write.g7b | 22 +++++----- src/shaders/render/exa_wm_write.g7i | 80 +++++++++++++++++++++++++++++++++++++ src/shaders/render/exa_wm_write.g8a | 59 +-------------------------- src/shaders/render/exa_wm_write.g8b | 22 +++++----- src/shaders/render/exa_wm_write.g9a | 58 +-------------------------- 7 files changed, 107 insertions(+), 196 deletions(-) create mode 100644 src/shaders/render/exa_wm_write.g7i diff --git a/src/shaders/render/Makefile.am b/src/shaders/render/Makefile.am index eef6108..1228366 100644 --- a/src/shaders/render/Makefile.am +++ b/src/shaders/render/Makefile.am @@ -59,7 +59,8 @@ INTEL_G6B = \ exa_wm_yuv_color_balance.g6b \ exa_wm_yuv_rgb.g6b -INTEL_G7I = $(INTEL_G4I) +INTEL_G7I = $(INTEL_G4I) \ + exa_wm_write.g7i INTEL_G7A = \ exa_wm_src_affine.g7a \ diff --git a/src/shaders/render/exa_wm_write.g7a b/src/shaders/render/exa_wm_write.g7a index 4b17929..f2eb0ea 100644 --- a/src/shaders/render/exa_wm_write.g7a +++ b/src/shaders/render/exa_wm_write.g7a @@ -23,61 +23,4 @@ */ include(`exa_wm.g4i') - -/* header */ -define(`data_port_msg_2_0', `g64') -define(`data_port_msg_2_1', `g65') -define(`data_port_msg_2_ind', `64') - -mov (8) data_port_msg_2_0<1>UD g0<8,8,1>UD {align1 mask_disable}; -mov (8) data_port_msg_2_1<1>UD g1<8,8,1>UD {align1 mask_disable}; - -/* - * Prepare data in g66-g67 for Red channel, g68-g69 for Green channel, - * g70-g71 for Blue and g72-g73 for Alpha channel - */ -define(`slot_r_00', `g66') -define(`slot_r_01', `g67') -define(`slot_g_00', `g68') -define(`slot_g_01', `g69') -define(`slot_b_00', `g70') -define(`slot_b_01', `g71') -define(`slot_a_00', `g72') -define(`slot_a_01', `g73') - -mov (8) slot_r_00<1>F src_sample_r_01<8,8,1>F { align1 mask_disable }; -mov (8) slot_r_01<1>F src_sample_r_23<8,8,1>F { align1 mask_disable }; - -mov (8) slot_g_00<1>F src_sample_g_01<8,8,1>F { align1 mask_disable }; -mov (8) slot_g_01<1>F src_sample_g_23<8,8,1>F { align1 mask_disable }; - -mov (8) slot_b_00<1>F src_sample_b_01<8,8,1>F { align1 mask_disable }; -mov (8) slot_b_01<1>F src_sample_b_23<8,8,1>F { align1 mask_disable }; - -mov (8) slot_a_00<1>F src_sample_a_01<8,8,1>F { align1 mask_disable }; -mov (8) slot_a_01<1>F src_sample_a_23<8,8,1>F { align1 mask_disable }; - -send (16) - data_port_msg_2_ind - null<1>UW - null - write ( - 0, /* binding table index */ - 16, /* last render target(1) + slots 15:0(0) + msg type simd16 single source(000) */ - 12, /* render target write */ - 0, /* ignore for Ivybridge */ - 1 /* header present */ - ) - mlen 10 - rlen 0 - { align1 EOT }; - -nop; -nop; -nop; -nop; -nop; -nop; -nop; -nop; - +include(`exa_wm_write.g7i') diff --git a/src/shaders/render/exa_wm_write.g7b b/src/shaders/render/exa_wm_write.g7b index 4f347cb..b0a1d07 100644 --- a/src/shaders/render/exa_wm_write.g7b +++ b/src/shaders/render/exa_wm_write.g7b @@ -1,14 +1,14 @@ - { 0x00600201, 0x28000021, 0x008d0000, 0x00000000 }, - { 0x00600201, 0x28200021, 0x008d0020, 0x00000000 }, - { 0x00600201, 0x284003bd, 0x008d01c0, 0x00000000 }, - { 0x00600201, 0x286003bd, 0x008d01e0, 0x00000000 }, - { 0x00600201, 0x288003bd, 0x008d0200, 0x00000000 }, - { 0x00600201, 0x28a003bd, 0x008d0220, 0x00000000 }, - { 0x00600201, 0x28c003bd, 0x008d0240, 0x00000000 }, - { 0x00600201, 0x28e003bd, 0x008d0260, 0x00000000 }, - { 0x00600201, 0x290003bd, 0x008d0280, 0x00000000 }, - { 0x00600201, 0x292003bd, 0x008d02a0, 0x00000000 }, - { 0x05800031, 0x20001ca8, 0x00000800, 0x940b1000 }, + { 0x00600201, 0x2e000021, 0x008d0000, 0x00000000 }, + { 0x00600201, 0x2e200021, 0x008d0020, 0x00000000 }, + { 0x00600201, 0x2e4003bd, 0x008d01c0, 0x00000000 }, + { 0x00600201, 0x2e6003bd, 0x008d01e0, 0x00000000 }, + { 0x00600201, 0x2e8003bd, 0x008d0200, 0x00000000 }, + { 0x00600201, 0x2ea003bd, 0x008d0220, 0x00000000 }, + { 0x00600201, 0x2ec003bd, 0x008d0240, 0x00000000 }, + { 0x00600201, 0x2ee003bd, 0x008d0260, 0x00000000 }, + { 0x00600201, 0x2f0003bd, 0x008d0280, 0x00000000 }, + { 0x00600201, 0x2f2003bd, 0x008d02a0, 0x00000000 }, + { 0x05800031, 0x20001ca8, 0x00000e00, 0x940b1000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, diff --git a/src/shaders/render/exa_wm_write.g7i b/src/shaders/render/exa_wm_write.g7i new file mode 100644 index 0000000..3fbb432 --- /dev/null +++ b/src/shaders/render/exa_wm_write.g7i @@ -0,0 +1,80 @@ +/* + * Copyright © 2010 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +/* header */ +define(`data_port_msg_2_0', `g112') +define(`data_port_msg_2_1', `g113') +define(`data_port_msg_2_ind', `112') + +mov (8) data_port_msg_2_0<1>UD g0<8,8,1>UD {align1 mask_disable}; +mov (8) data_port_msg_2_1<1>UD g1<8,8,1>UD {align1 mask_disable}; + +/* + * Prepare data in g114-g115 for Red channel, g116-g117 for Green channel, + * g118-g119 for Blue and g120-g121 for Alpha channel + */ +define(`slot_r_00', `g114') +define(`slot_r_01', `g115') +define(`slot_g_00', `g116') +define(`slot_g_01', `g117') +define(`slot_b_00', `g118') +define(`slot_b_01', `g119') +define(`slot_a_00', `g120') +define(`slot_a_01', `g121') + +mov (8) slot_r_00<1>F src_sample_r_01<8,8,1>F { align1 mask_disable }; +mov (8) slot_r_01<1>F src_sample_r_23<8,8,1>F { align1 mask_disable }; + +mov (8) slot_g_00<1>F src_sample_g_01<8,8,1>F { align1 mask_disable }; +mov (8) slot_g_01<1>F src_sample_g_23<8,8,1>F { align1 mask_disable }; + +mov (8) slot_b_00<1>F src_sample_b_01<8,8,1>F { align1 mask_disable }; +mov (8) slot_b_01<1>F src_sample_b_23<8,8,1>F { align1 mask_disable }; + +mov (8) slot_a_00<1>F src_sample_a_01<8,8,1>F { align1 mask_disable }; +mov (8) slot_a_01<1>F src_sample_a_23<8,8,1>F { align1 mask_disable }; + +send (16) + data_port_msg_2_ind + null<1>UW + null + write ( + 0, /* binding table index */ + 16, /* last render target(1) + slots 15:0(0) + msg type simd16 single source(000) */ + 12, /* render target write */ + 0, /* ignore for Ivybridge */ + 1 /* header present */ + ) + mlen 10 + rlen 0 + { align1 EOT }; + +nop; +nop; +nop; +nop; +nop; +nop; +nop; +nop; diff --git a/src/shaders/render/exa_wm_write.g8a b/src/shaders/render/exa_wm_write.g8a index e6da9b6..6c386af 100644 --- a/src/shaders/render/exa_wm_write.g8a +++ b/src/shaders/render/exa_wm_write.g8a @@ -23,61 +23,4 @@ */ include(`exa_wm.g4i') - -/* header */ -define(`data_port_msg_2_0', `g64') -define(`data_port_msg_2_1', `g65') -define(`data_port_msg_2_ind', `64') - -mov (8) data_port_msg_2_0<1>UD g0<8,8,1>UD {align1 mask_disable}; -mov (8) data_port_msg_2_1<1>UD g1<8,8,1>UD {align1 mask_disable}; - -/* - * Prepare data in g66-g67 for Red channel, g68-g69 for Green channel, - * g70-g71 for Blue and g72-g73 for Alpha channel - */ -define(`slot_r_00', `g66') -define(`slot_r_01', `g67') -define(`slot_g_00', `g68') -define(`slot_g_01', `g69') -define(`slot_b_00', `g70') -define(`slot_b_01', `g71') -define(`slot_a_00', `g72') -define(`slot_a_01', `g73') - -mov (8) slot_r_00<1>F src_sample_r_01<8,8,1>F { align1 mask_disable }; -mov (8) slot_r_01<1>F src_sample_r_23<8,8,1>F { align1 mask_disable }; - -mov (8) slot_g_00<1>F src_sample_g_01<8,8,1>F { align1 mask_disable }; -mov (8) slot_g_01<1>F src_sample_g_23<8,8,1>F { align1 mask_disable }; - -mov (8) slot_b_00<1>F src_sample_b_01<8,8,1>F { align1 mask_disable }; -mov (8) slot_b_01<1>F src_sample_b_23<8,8,1>F { align1 mask_disable }; - -mov (8) slot_a_00<1>F src_sample_a_01<8,8,1>F { align1 mask_disable }; -mov (8) slot_a_01<1>F src_sample_a_23<8,8,1>F { align1 mask_disable }; - -send (16) - data_port_msg_2_ind - null<1>UW - null - write ( - 0, /* binding table index */ - 16, /* last render target(1) + slots 15:0(0) + msg type simd16 single source(000) */ - 12, /* render target write */ - 0, /* ignore for Ivybridge */ - 1 /* header present */ - ) - mlen 10 - rlen 0 - { align1 EOT }; - -nop; -nop; -nop; -nop; -nop; -nop; -nop; -nop; - +include(`exa_wm_write.g7i') diff --git a/src/shaders/render/exa_wm_write.g8b b/src/shaders/render/exa_wm_write.g8b index 822578d..a320f46 100644 --- a/src/shaders/render/exa_wm_write.g8b +++ b/src/shaders/render/exa_wm_write.g8b @@ -1,14 +1,14 @@ - { 0x00600001, 0x2800020c, 0x008d0000, 0x00000000 }, - { 0x00600001, 0x2820020c, 0x008d0020, 0x00000000 }, - { 0x00600001, 0x28403aec, 0x008d01c0, 0x00000000 }, - { 0x00600001, 0x28603aec, 0x008d01e0, 0x00000000 }, - { 0x00600001, 0x28803aec, 0x008d0200, 0x00000000 }, - { 0x00600001, 0x28a03aec, 0x008d0220, 0x00000000 }, - { 0x00600001, 0x28c03aec, 0x008d0240, 0x00000000 }, - { 0x00600001, 0x28e03aec, 0x008d0260, 0x00000000 }, - { 0x00600001, 0x29003aec, 0x008d0280, 0x00000000 }, - { 0x00600001, 0x29203aec, 0x008d02a0, 0x00000000 }, - { 0x05800031, 0x20000a40, 0x0e000800, 0x940b1000 }, + { 0x00600001, 0x2e00020c, 0x008d0000, 0x00000000 }, + { 0x00600001, 0x2e20020c, 0x008d0020, 0x00000000 }, + { 0x00600001, 0x2e403aec, 0x008d01c0, 0x00000000 }, + { 0x00600001, 0x2e603aec, 0x008d01e0, 0x00000000 }, + { 0x00600001, 0x2e803aec, 0x008d0200, 0x00000000 }, + { 0x00600001, 0x2ea03aec, 0x008d0220, 0x00000000 }, + { 0x00600001, 0x2ec03aec, 0x008d0240, 0x00000000 }, + { 0x00600001, 0x2ee03aec, 0x008d0260, 0x00000000 }, + { 0x00600001, 0x2f003aec, 0x008d0280, 0x00000000 }, + { 0x00600001, 0x2f203aec, 0x008d02a0, 0x00000000 }, + { 0x05800031, 0x20000a40, 0x0e000e00, 0x940b1000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, diff --git a/src/shaders/render/exa_wm_write.g9a b/src/shaders/render/exa_wm_write.g9a index 5275cdc..d735efd 100644 --- a/src/shaders/render/exa_wm_write.g9a +++ b/src/shaders/render/exa_wm_write.g9a @@ -23,60 +23,4 @@ */ include(`exa_wm.g4i') - -/* header */ -define(`data_port_msg_2_0', `g112') -define(`data_port_msg_2_1', `g113') -define(`data_port_msg_2_ind', `112') - -mov (8) data_port_msg_2_0<1>UD g0<8,8,1>UD {align1 mask_disable}; -mov (8) data_port_msg_2_1<1>UD g1<8,8,1>UD {align1 mask_disable}; - -/* - * Prepare data in g114-g115 for Red channel, g116-g117 for Green channel, - * g118-g119 for Blue and g120-g121 for Alpha channel - */ -define(`slot_r_00', `g114') -define(`slot_r_01', `g115') -define(`slot_g_00', `g116') -define(`slot_g_01', `g117') -define(`slot_b_00', `g118') -define(`slot_b_01', `g119') -define(`slot_a_00', `g120') -define(`slot_a_01', `g121') - -mov (8) slot_r_00<1>F src_sample_r_01<8,8,1>F { align1 mask_disable }; -mov (8) slot_r_01<1>F src_sample_r_23<8,8,1>F { align1 mask_disable }; - -mov (8) slot_g_00<1>F src_sample_g_01<8,8,1>F { align1 mask_disable }; -mov (8) slot_g_01<1>F src_sample_g_23<8,8,1>F { align1 mask_disable }; - -mov (8) slot_b_00<1>F src_sample_b_01<8,8,1>F { align1 mask_disable }; -mov (8) slot_b_01<1>F src_sample_b_23<8,8,1>F { align1 mask_disable }; - -mov (8) slot_a_00<1>F src_sample_a_01<8,8,1>F { align1 mask_disable }; -mov (8) slot_a_01<1>F src_sample_a_23<8,8,1>F { align1 mask_disable }; - -send (16) - data_port_msg_2_ind - null<1>UW - null - write ( - 0, /* binding table index */ - 16, /* last render target(1) + slots 15:0(0) + msg type simd16 single source(000) */ - 12, /* render target write */ - 0, /* ignore for Ivybridge */ - 1 /* header present */ - ) - mlen 10 - rlen 0 - { align1 EOT }; - -nop; -nop; -nop; -nop; -nop; -nop; -nop; -nop; +include(`exa_wm_write.g7i') -- 1.9.1 _______________________________________________ Libva mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/libva
