Public bug reported:
An upstream commit added Intel cpu model/microcode checks to disable
TSC_DEADLINE due to cpu errata:
commit bd9240a18edfbfa72e957fc2ba831cf1f13ea073
Author: Peter Zijlstra <pet...@infradead.org>
Date: Wed May 31 17:52:03 2017 +0200
x86/apic: Add TSC_DEADLINE quirk due to errata
That commit is included in the Ubuntu kernels starting at artful v4.13.
However, most hypervisors virtualize TSC deadline timer (and therefore
it isn't affected by Intel CPU errata inside the guest), and even if any
hypervisors directly exposed the hardware TSC deadline timer, the guests
cannot update CPU microcode and therefore it's the hypervisor's job to
disable/hide/virtualize the TSC deadline timer from the guest.
This upstream commit skips the microcode check to disable the TSC
deadline timer if it detects it's running under a hypervisor:
commit cc6afe2240298049585e86b1ade85efc8a7f225d
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: Tue Oct 10 12:12:57 2017 +0200
x86/apic: Silence "FW_BUG TSC_DEADLINE disabled due to Errata" on
hypervisors
** Affects: linux (Ubuntu)
Importance: Medium
Assignee: Dan Streetman (ddstreet)
Status: In Progress
** Affects: linux (Ubuntu Artful)
Importance: Medium
Assignee: Dan Streetman (ddstreet)
Status: In Progress
** Affects: linux (Ubuntu Bb-series)
Importance: Medium
Assignee: Dan Streetman (ddstreet)
Status: In Progress
** Changed in: linux (Ubuntu)
Status: New => Fix Released
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https://bugs.launchpad.net/bugs/1724912
Title:
TSC_DEADLINE incorrectly disabled inside virtual guests
Status in linux package in Ubuntu:
In Progress
Status in linux source package in Artful:
In Progress
Status in linux source package in bb-series:
In Progress
Bug description:
An upstream commit added Intel cpu model/microcode checks to disable
TSC_DEADLINE due to cpu errata:
commit bd9240a18edfbfa72e957fc2ba831cf1f13ea073
Author: Peter Zijlstra <pet...@infradead.org>
Date: Wed May 31 17:52:03 2017 +0200
x86/apic: Add TSC_DEADLINE quirk due to errata
That commit is included in the Ubuntu kernels starting at artful
v4.13.
However, most hypervisors virtualize TSC deadline timer (and therefore
it isn't affected by Intel CPU errata inside the guest), and even if
any hypervisors directly exposed the hardware TSC deadline timer, the
guests cannot update CPU microcode and therefore it's the hypervisor's
job to disable/hide/virtualize the TSC deadline timer from the guest.
This upstream commit skips the microcode check to disable the TSC
deadline timer if it detects it's running under a hypervisor:
commit cc6afe2240298049585e86b1ade85efc8a7f225d
Author: Paolo Bonzini <pbonz...@redhat.com>
Date: Tue Oct 10 12:12:57 2017 +0200
x86/apic: Silence "FW_BUG TSC_DEADLINE disabled due to Errata" on
hypervisors
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