https://bugs.kde.org/show_bug.cgi?id=377966
Reimar Döffinger <k...@reimardoeffinger.de> changed:
What |Removed |Added
----------------------------------------------------------------------------
CC| |k...@reimardoeffinger.de
--- Comment #9 from Reimar Döffinger <k...@reimardoeffinger.de> ---
>From https://github.com/LouisBrunner/valgrind-macos/issues/56 :
A quick hack to implement the instruction.
It does not address other points raised, like reading DCZID_EL0 maybe should
flag the instruction as supported and indicate the size.
I felt it safer to discourage software from using this instruction by keeping
the current implementation reporting it as not supported.
Patch for reference for anyone who wants to work on something clean enough to
merge:
diff --git a/VEX/priv/guest_arm64_toIR.c b/VEX/priv/guest_arm64_toIR.c
index 51c949def..9d04c4303 100644
--- a/VEX/priv/guest_arm64_toIR.c
+++ b/VEX/priv/guest_arm64_toIR.c
@@ -7948,6 +7948,30 @@ Bool dis_ARM64_branch_etc(/*MB_OUT*/DisResult* dres,
UInt insn,
return True;
}
+ /* ------------------ DC_ZVA ------------------ */
+ /* D5 0B 74 001 Rt dc zva, rT
+ */
+ if ((INSN(31,0) & 0xFFFFFFE0) == 0xD50B7420) {
+ /* Exactly the same scheme as for IC IVAU, except we observe the
+ dMinLine size. */
+ /* We will always be provided with a valid dMinLine value. */
+ vassert(archinfo->arm64_dMinLine_lg2_szB >= 2
+ && archinfo->arm64_dMinLine_lg2_szB <= 17);
+ /* Round the requested address, in rT, down to the start of the
+ containing block. */
+ UInt tt = INSN(4,0);
+ ULong lineszB = 1ULL << archinfo->arm64_dMinLine_lg2_szB;
+ IRTemp addr = newTemp(Ity_I64);
+ assign( addr, binop( Iop_And64,
+ getIReg64orZR(tt),
+ mkU64(~(lineszB - 1))) );
+ for (ULong o = 0; o < lineszB; o += 8)
+ {
+ storeLE(binop(Iop_Add64,mkexpr(addr),mkU64(o)), mkU64(0));
+ }
+ DIP("dc zva, %s\n", nameIReg64orZR(tt));
+ return True;
+ }
/* ------------------ DC_CVAU ------------------ */
/* D5 0B 7B 001 Rt dc cvau, rT
D5 0B 7E 001 Rt dc civac, rT
--
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