https://bugs.kde.org/show_bug.cgi?id=432387
Julian Seward <jsew...@acm.org> changed:
What |Removed |Added
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CC| |jsew...@acm.org
--- Comment #3 from Julian Seward <jsew...@acm.org> ---
Nice work! The following look OK to land as-is:
Subject: [PATCH 01/13] s390x: Misc-insn-3, bitwise logical 3-way instructions
Subject: [PATCH 02/13] s390x: Misc-insn-3, "select" instructions
Subject: [PATCH 03/13] s390x: Misc-insn-3, new POPCNT variant
Subject: [PATCH 04/13] s390x: Misc-insn-3, MVCRL
Subject: [PATCH 06/13] s390x: Vec-enh-2, extend VSL, VSRA, and VSRL
Subject: [PATCH 09/13] s390x: Vec-enh-2, VSLD and VSRD
Subject: [PATCH 10/13] s390x: Vec-enh-2, VSTRS
Subject: [PATCH 11/13] s390x: Mark arch13 features as supported
Subject: [PATCH 12/13] s390x: Vec-enh-2, test cases
Subject: [PATCH 13/13] s390x: Wrap up misc-insn-3 and vec-enh-2 support
For patches 05/13 and 07/13, I have a couple of queries/comments, but nothing
serious. Providing those assertions won't fail and that there's no build-time
dependency problems for the test cases, OK to land these two too.
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Subject: [PATCH 05/13] s390x: Misc-insn-3, test case
none/tests/s390x/Makefile.am
@@ -19,7 +19,8 @@ INSN_TESTS = clc clcle cvb cvd icm lpr tcxb lam_stam xc mvst
add sub mul \
spechelper-ltr spechelper-or \
spechelper-icm-1 spechelper-icm-2 spechelper-tmll \
spechelper-tm laa vector lsc2 ppno vector_string vector_integer \
- vector_float add-z14 sub-z14 mul-z14 bic
+ vector_float add-z14 sub-z14 mul-z14 bic \
+ misc3
Is `misc3` safe to always-build? Or would it require gating on assembler
features, in the style of "if BUILD_DFP_TESTS .." just below?
.. ah .. later .. I see misc3.c doesn't require any assembler support,
since it just does `insn rrf,0x" #opcode "0000,%[out],%[a],%[b],0\n\t"`.
diff --git a/none/tests/s390x/misc3.vgtest b/none/tests/s390x/misc3.vgtest
new file mode 100644
index 000000000..d051a06bd
--- /dev/null
+++ b/none/tests/s390x/misc3.vgtest
@@ -0,0 +1 @@
+prog: misc3
Similarly, does this require gating on host hwcaps? Looking at your _toIR.c
implementation, maybe not, since that appears to be down-translating (I mean,
translating from the z15 dialect into IR which will be re-emitted as
instructions for some earlier zSeries CPU). I suppose this means that on
older platforms, it will be possible to compile this test, and run it on V,
but not to run it natively.
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Subject: [PATCH 07/13] s390x: Vec-enh-2, extend VCDG, VCDLG, VCGD, and VCLGD
+ s390_insn_assert("vcdlg", m3 == 2 || m3 == 3);
(multiple times)
This will fail only on internal logic errors, correct? .. it can't fail only
because the insn can't be decoded, right?
Subject: [PATCH 08/13] s390x: Vec-enh-2, VLBR and friends
+++ b/VEX/priv/host_s390_isel.c
+ case Iop_Perm8x16:
Seeing use of Iop_Perm8x16 made me wonder if it had a definition that
is independent of the guest/host endianness .. and, no it doesn't:
libvex_ir.h says:
for i in 0 .. 15 . result[i] = argL[ argR[i] ]
so the meaning of "[n]" is itself ambiguous. Anyways, no need to
change anything in your code.
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