https://bugs.kde.org/show_bug.cgi?id=468575
--- Comment #46 from Richard Jones <rjo...@redhat.com> ---
(In reply to Mark Wielaard from comment #43)
> Assuming fence and fence.tso are basically the same thing
> (which they might not be) then the following seems to fix it:
Normal memory model is Arm-like (ie. quite relaxed). RISC-V processors with
the TSO (total store ordering) extension ("Ztso") behave more like the x86
memory model. FENCE.TSO is a fence instruction that is like FENCE but uses
total store ordering.
Ztso: https://github.com/riscv/riscv-isa-manual/blob/main/src/ztso-st-ext.adoc
FENCE.TSO:
https://riscv-software-src.github.io/riscv-unified-db/manual/html/isa/20240411/insts/fence.html
> diff --git a/VEX/priv/guest_riscv64_toIR.c b/VEX/priv/guest_riscv64_toIR.c
> index 93ea5a173..a4f4a1907 100644
> --- a/VEX/priv/guest_riscv64_toIR.c
> +++ b/VEX/priv/guest_riscv64_toIR.c
> @@ -1610,7 +1610,8 @@ static Bool dis_RV64I(/*MB_OUT*/ DisResult* dres,
> }
>
> /* ------------------------ fence ------------------------ */
> - if (INSN(19, 0) == 0b00000000000000001111 && INSN(31, 28) == 0b0000) {
> + if (INSN(19, 0) == 0b00000000000000001111
> + && (INSN(31, 28) == 0b0000 || INSN(31, 28) == 0b1000)) {
> UInt succ = INSN(23, 20);
> UInt pred = INSN(27, 24);
> stmt(irsb, IRStmt_MBE(Imbe_Fence));
Does valgrind have anything like Arm vs x86 memory models? If it does then I
suspect the above will be wrong.
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