D1 is a RISC-V SoC from Allwinner's sunxi family. This series adds IOMMU binding and driver support.
One piece is still missing to use the IOMMU for DMA allocations: a call to iommu_setup_dma_ops(). On ARM64 this is handled by the architecture's code. RISC-V does not currently select ARCH_HAS_SETUP_DMA_OPS, but it will once Zicbom support[1] is merged. [1]: https://lore.kernel.org/lkml/[email protected]/ So I cannot follow virtio-iommu.c and call iommu_setup_dma_ops() when ARCH_HAS_SETUP_DMA_OPS=n. However, if I apply the following patch on top of Heiko's non-coherent DMA series, the display engine successfully uses the IOMMU to allocate its framebuffer: --- a/arch/riscv/mm/dma-noncoherent.c +++ b/arch/riscv/mm/dma-noncoherent.c @@ -6,6 +6,7 @@ */ #include <linux/dma-direct.h> +#include <linux/dma-iommu.h> #include <linux/dma-map-ops.h> #include <linux/mm.h> @@ -53,4 +54,7 @@ { /* If a specific device is dma-coherent, set it here */ dev->dma_coherent = coherent; + + if (iommu) + iommu_setup_dma_ops(dev, dma_base, dma_base + size - 1); } Samuel Holland (5): dt-bindings: iommu: sun50i: Add compatible for Allwinner D1 iommu/sun50i: Support variants without an external reset iommu/sun50i: Ensure bypass is disabled iommu/sun50i: Add support for the D1 variant iommu/sun50i: Ensure the IOMMU can be used for DMA .../iommu/allwinner,sun50i-h6-iommu.yaml | 16 +++++++++++-- drivers/iommu/Kconfig | 1 + drivers/iommu/sun50i-iommu.c | 24 +++++++++++++++++-- 3 files changed, 37 insertions(+), 4 deletions(-) -- 2.35.1 _______________________________________________ iommu mailing list [email protected] https://lists.linuxfoundation.org/mailman/listinfo/iommu
