Hi Joerg, Thanks a lot for reviewing this patchset.
On 11/27/15 at 12:38pm, Joerg Roedel wrote: > On Fri, Nov 06, 2015 at 08:10:42PM +0800, Baoquan He wrote: > > This is v2 draft patch set. It mainly functions as the following steps: > > > > 1. Checking if it's in kdump kernel and previously enabled > > 2. If yes do below operatons: > > a. Do not disable amd iommu and do not touch dev tables before coping > > old dev tables > > b. Copy dev table from old kernel and set the old domain id in > > amd_iommu_pd_alloc_bitmap > > c. Copy irq tables from old kernel > > d. Copy command buffer and event buffer > > e. Don't call update_domain() to set domain->pt_root to dev entries > > before device driver initialization. > > f. Reset the pre-enabled status in case IOMMU_DMA_OPS of state_next(). > > > > Existed problems: > > "Existed" means here these problems are gone? It should be existing, I used wrong word. > > > > > 1. It always prints the following message whenever do a flush: > > > > "AMD-Vi: Completion-Wait loop timed out" > > > > 2. Maybe there's someing wrong with the old irq remapping handling, the > > hard disk can't be brought up > > successfully. You can check the attached kdump kernel boot log with this > > patchset applied. > > The reason is most likely that you didn't re-initialize the command > buffer before doing any flushes. The you see the above Completion-Wait > loop timeouts. Yeah, you are right. I tried many kinds of calling, but didn't try calling iommu_enable_command_buffer() earlier than copy_dev_tables(). Now I tried calling iommu_enable_command_buffer() and iommu_enable_event_buffer() earlier than copy_dev_tables(), message "AMD-Vi: Completion-Wait loop timed out" is gone on my AMD IOMMU V1 machine. On my AMD A10-7850K which is AMD IOMMU V2 it still print that message, I am debugging. And problem that sata disk can't be brought up still exist. Thanks Baoquan _______________________________________________ iommu mailing list [email protected] https://lists.linuxfoundation.org/mailman/listinfo/iommu
