Hi Geert,
On Monday 31 March 2014 10:52:28 Geert Uytterhoeven wrote:
> On Sat, Mar 29, 2014 at 12:36 AM, Laurent Pinchart wrote:
> > + ipmmu_sy0: mmu@e6280800 {
> > + compatible = "renesas,ipmmu-vmsa";
> > + reg = <0 0xe6280800 0 0x800>;
>
> Shouldn't this be "reg = <0 0xe6280000 0 0x1000>", i.e. expose both
> banks?
>
> Is there any specific reason you're using the second bank of registers?
> These may read as zero, depending on the SoC mode.
That's a very good question, and I have no clear answer. According to the
datasheet the second bank of registers is an alias for the non-secure IPMMU
registers. It looks like we're running in secure mode (that's what I assume
the "CPU: All CPU(s) started in SVC mode." kernel log message means), and the
secure IPMMU didn't seem to be functional when I've tested it.
This requires more investigation, but I'm not familiar with secure mode, and
the IPMMU documentation is really sparse in that area.
> > + interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>;
> > + status = "disabled";
> > + };
>
> Same comment for the other nodes.
--
Regards,
Laurent Pinchart
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