TLB_FLUSH_ASID bit range depends on the number of asids to support other number than the current 4, especially for a new Tegra124. Based on Terje's internal patch.
Signed-off-by: Hiroshi Doyu <[email protected]> Cc: Terje Bergstrom <[email protected]> --- drivers/iommu/tegra-smmu.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index 9b81e3a..535b14a 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -92,11 +92,14 @@ enum { #define SMMU_TLB_FLUSH_VA_MATCH_ALL 0 #define SMMU_TLB_FLUSH_VA_MATCH_SECTION 2 #define SMMU_TLB_FLUSH_VA_MATCH_GROUP 3 -#define SMMU_TLB_FLUSH_ASID_SHIFT 29 +#define SMMU_TLB_FLUSH_ASID_SHIFT_BASE 31 #define SMMU_TLB_FLUSH_ASID_MATCH_DISABLE 0 #define SMMU_TLB_FLUSH_ASID_MATCH_ENABLE 1 #define SMMU_TLB_FLUSH_ASID_MATCH_SHIFT 31 +#define SMMU_TLB_FLUSH_ASID_SHIFT(as) \ + (SMMU_TLB_FLUSH_ASID_SHIFT_BASE - __ffs((as)->smmu->num_as)) + #define SMMU_PTC_FLUSH 0x34 #define SMMU_PTC_FLUSH_TYPE_ALL 0 #define SMMU_PTC_FLUSH_TYPE_ADR 1 @@ -563,7 +566,7 @@ static void flush_ptc_and_tlb(struct smmu_device *smmu, val = tlb_flush_va | SMMU_TLB_FLUSH_ASID_MATCH__ENABLE | - (as->asid << SMMU_TLB_FLUSH_ASID_SHIFT); + (as->asid << SMMU_TLB_FLUSH_ASID_SHIFT(as)); smmu_write(smmu, val, SMMU_TLB_FLUSH); FLUSH_SMMU_REGS(smmu); } @@ -730,7 +733,7 @@ static int alloc_pdir(struct smmu_as *as) val = SMMU_TLB_FLUSH_VA_MATCH_ALL | SMMU_TLB_FLUSH_ASID_MATCH__ENABLE | - (as->asid << SMMU_TLB_FLUSH_ASID_SHIFT); + (as->asid << SMMU_TLB_FLUSH_ASID_SHIFT(as)); smmu_write(smmu, val, SMMU_TLB_FLUSH); FLUSH_SMMU_REGS(as->smmu); -- 1.8.1.5 _______________________________________________ iommu mailing list [email protected] https://lists.linuxfoundation.org/mailman/listinfo/iommu
