Pass dev_priv to all instances of HAS_RESOURCE_STREAMER() and
HAS_CORE_RING_FREQ(), and make the macros use INTEL_GEN().

Signed-off-by: David Weinehall <[email protected]>
---
 drivers/gpu/drm/i915/i915_drv.c            |  2 +-
 drivers/gpu/drm/i915/i915_drv.h            | 11 ++++++-----
 drivers/gpu/drm/i915/i915_gem_execbuffer.c |  2 +-
 3 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index eee2fdba2e27..cef3c34b15ab 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -344,7 +344,7 @@ static int i915_getparam(struct drm_device *dev, void *data,
                value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv);
                break;
        case I915_PARAM_HAS_RESOURCE_STREAMER:
-               value = HAS_RESOURCE_STREAMER(dev);
+               value = HAS_RESOURCE_STREAMER(dev_priv);
                break;
        case I915_PARAM_HAS_EXEC_SOFTPIN:
                value = 1;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e7c6d95edcdf..ff8df2995df8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2802,12 +2802,13 @@ struct drm_i915_cmd_table {
 #define HAS_GUC_UCODE(dev)     (HAS_GUC(dev))
 #define HAS_GUC_SCHED(dev)     (HAS_GUC(dev))
 
-#define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
-                                   INTEL_INFO(dev)->gen >= 8)
+#define HAS_RESOURCE_STREAMER(dev_priv)        (IS_HASWELL(dev_priv) || \
+                                        INTEL_GEN(dev_priv) >= 8)
 
-#define HAS_CORE_RING_FREQ(dev)        (INTEL_INFO(dev)->gen >= 6 && \
-                                !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
-                                !IS_BROXTON(dev))
+#define HAS_CORE_RING_FREQ(dev_priv)   (INTEL_GEN(dev_priv) >= 6 && \
+                                        !IS_VALLEYVIEW(dev_priv) && \
+                                        !IS_CHERRYVIEW(dev_priv) && \
+                                        !IS_BROXTON(dev_priv))
 
 #define HAS_POOLED_EU(dev_priv)        (__INTEL_INFO(dev_priv)->has_pooled_eu)
 
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c 
b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 6a94d8723770..be85c0325ddf 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1651,7 +1651,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
        }
 
        if (args->flags & I915_EXEC_RESOURCE_STREAMER) {
-               if (!HAS_RESOURCE_STREAMER(dev)) {
+               if (!HAS_RESOURCE_STREAMER(dev_priv)) {
                        DRM_DEBUG("RS is only allowed for Haswell, Gen8 and 
above\n");
                        return -EINVAL;
                }
-- 
2.9.3

_______________________________________________
Intel-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Reply via email to