On Wed, Jan 13, 2016 at 05:28:19PM +0000, Arun Siluvery wrote:
> /* i915_irq.c */
> void i915_queue_hangcheck(struct drm_device *dev);
> -__printf(4, 5)
> -void i915_handle_error(struct drm_device *dev, u32 engine_mask, bool wedged,
> - const char *fmt, ...);
> +__printf(5, 6)
> +void i915_handle_error(struct drm_device *dev, u32 engine_mask,
> + bool watchdog, bool wedged, const char *fmt, ...);
>
> extern void intel_irq_init(struct drm_i915_private *dev_priv);
> int intel_irq_install(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 8937c82..0710724 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2726,6 +2726,7 @@ static void i915_report_and_clear_eir(struct drm_device
> *dev)
> * If a previous engine reset was attempted too recently
> * or if one of the current engine resets fails we fall
> * back to legacy full GPU reset.
> + * @watchdog: true = Engine hang detected by hardware
> watchdog.
> * @wedged: true = Hang detected, invoke hang recovery.
A bitmask and 2 booleans? Whilst this isn't going to be the most widely
used of functions, those parameters are just inviting trouble.
> * @fmt, ...: Error message describing reason for error.
> *
> @@ -2737,8 +2738,8 @@ static void i915_report_and_clear_eir(struct drm_device
> *dev)
> * reset the associated engine. Failing that, try to fall back to legacy
> * full GPU reset recovery mode.
> */
> -void i915_handle_error(struct drm_device *dev, u32 engine_mask, bool wedged,
> - const char *fmt, ...)
> +void i915_handle_error(struct drm_device *dev, u32 engine_mask,
> + bool watchdog, bool wedged, const char *fmt, ...)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> va_list args;
> @@ -2776,20 +2777,27 @@ void i915_handle_error(struct drm_device *dev, u32
> engine_mask, bool wedged,
> u32 i;
>
> for_each_ring(engine, dev_priv, i) {
> - u32 now, last_engine_reset_timediff;
Oops skipped a patch, I'll be back.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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