On 09/18/2015 10:03 AM, [email protected] wrote: > From: Ville Syrjälä <[email protected]> > > Signed-off-by: Ville Syrjälä <[email protected]> > --- > drivers/gpu/drm/i915/i915_irq.c | 31 +++++++++++++++++-------------- > 1 file changed, 17 insertions(+), 14 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 16948b2..24f68de 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -139,27 +139,30 @@ static const u32 hpd_bxt[HPD_NUM_PINS] = { > /* > * We should clear IMR at preinstall/uninstall, and just check at > postinstall. > */ > -#define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \ > - u32 val = I915_READ(reg); \ > - if (val) { \ > - WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \ > - (reg), val); \ > - I915_WRITE((reg), 0xffffffff); \ > - POSTING_READ(reg); \ > - I915_WRITE((reg), 0xffffffff); \ > - POSTING_READ(reg); \ > - } \ > -} while (0) > +static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv, u32 > reg) > +{ > + u32 val = I915_READ(reg); > + > + if (val == 0) > + return; > + > + WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", > + reg, val); > + I915_WRITE(reg, 0xffffffff); > + POSTING_READ(reg); > + I915_WRITE(reg, 0xffffffff); > + POSTING_READ(reg); > +} > > #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \ > - GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \ > + gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \ > I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \ > I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \ > POSTING_READ(GEN8_##type##_IMR(which)); \ > } while (0) > > #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \ > - GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \ > + gen5_assert_iir_is_zero(dev_priv, type##IIR); \ > I915_WRITE(type##IER, (ier_val)); \ > I915_WRITE(type##IMR, (imr_val)); \ > POSTING_READ(type##IMR); \ > @@ -3276,7 +3279,7 @@ static void ibx_irq_postinstall(struct drm_device *dev) > else > mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT; > > - GEN5_ASSERT_IIR_IS_ZERO(SDEIIR); > + gen5_assert_iir_is_zero(dev_priv, SDEIIR); > I915_WRITE(SDEIMR, ~mask); > } > >
Reviewed-by: Jesse Barnes <[email protected]> _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
