On Fri, Jul 31, 2015 at 11:32:53AM +0530, Sivakumar Thulasimani wrote:
> From: "Thulasimani,Sivakumar" <[email protected]>
>
> This patch removes 5.4Gbps from supported link rate for CHV since
> it is not supported in it.
>
> Signed-off-by: Sivakumar Thulasimani <[email protected]>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index d9fb7a8..4e53433 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1186,8 +1186,9 @@ intel_dp_source_rates(struct drm_device *dev, const int
> **source_rates)
>
> *source_rates = default_rates;
>
> - if (IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0)
> - /* WaDisableHBR2:skl */
> + /* WaDisableHBR2:skl */
> + if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) ||
> + IS_CHERRYVIEW(dev))
> return (DP_LINK_BW_2_7 >> 3) + 1;
> else if (INTEL_INFO(dev)->gen >= 8 ||
> (IS_HASWELL(dev) && !IS_HSW_ULX(dev)))
I would suggest reordering this a bit. Something likle this perhaps:
/* WaDisableHBR2:skl */
if (IS_SKYLAKE && ...)
return (DP_LINK_BW_2_7 >> 3) + 1;
if ((IS_HASWELL && !IS_HSW_ULX) || IS_BROADWELL || gen >= 9)
return (DP_LINK_BW_5_4 >> 3) + 1;
else
return (DP_LINK_BW_2_7 >> 3) + 1;
IMO that makes it easier to see exactly which platforms support
HBR2, and it keeps the SKL w/a separated neatly for easy removal in the
near future (I'm assuming we want to kill the w/a based on the fact that
it's for an early stepping).
--
Ville Syrjälä
Intel OTC
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