On Tue, May 26, 2015 at 08:22:39PM +0300, [email protected] wrote:
> From: Ville Syrjälä <[email protected]>
>
> Expecting CHV power wells to be just an extended versions of the VLV
> power wells, a bunch of commented out power wells were added in
> anticipation when Punit folks would implement it all. Turns out they
> never did, and instead CHV has fewer power wells than VLV. Rip out all
> the #if 0'ed junk that's not needed.
>
> v2: Rename the "pipe-a" well to "display" to match VLV
> Clarify the pipe A power well relationship to pipes B and C (Deepak)
>
> Reviewed-by: Deepak S <[email protected]>
> Signed-off-by: Ville Syrjälä <[email protected]>
Merged patches 1&2 from this series, thanks.
Btw did I not pull them in because of conflicts (since the other part of
the original series aren't ready) or because I missed them?
Thanks, Daniel
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 --
> drivers/gpu/drm/i915/intel_runtime_pm.c | 98
> ++-------------------------------
> 2 files changed, 4 insertions(+), 98 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fb49989..f5edb35 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -595,10 +595,6 @@ enum punit_power_well {
> PUNIT_POWER_WELL_DPIO_RX0 = 10,
> PUNIT_POWER_WELL_DPIO_RX1 = 11,
> PUNIT_POWER_WELL_DPIO_CMN_D = 12,
> - /* FIXME: guesswork below */
> - PUNIT_POWER_WELL_DPIO_TX_D_LANES_01 = 13,
> - PUNIT_POWER_WELL_DPIO_TX_D_LANES_23 = 14,
> - PUNIT_POWER_WELL_DPIO_RX2 = 15,
>
> PUNIT_POWER_WELL_NUM,
> };
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 720b0c6..1a45385 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -1233,18 +1233,6 @@ void intel_display_power_put(struct drm_i915_private
> *dev_priv,
> BIT(POWER_DOMAIN_AUX_C) | \
> BIT(POWER_DOMAIN_INIT))
>
> -#define CHV_PIPE_A_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PIPE_A) | \
> - BIT(POWER_DOMAIN_INIT))
> -
> -#define CHV_PIPE_B_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PIPE_B) | \
> - BIT(POWER_DOMAIN_INIT))
> -
> -#define CHV_PIPE_C_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PIPE_C) | \
> - BIT(POWER_DOMAIN_INIT))
> -
> #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
> BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
> BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
> @@ -1260,17 +1248,6 @@ void intel_display_power_put(struct drm_i915_private
> *dev_priv,
> BIT(POWER_DOMAIN_AUX_D) | \
> BIT(POWER_DOMAIN_INIT))
>
> -#define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
> - BIT(POWER_DOMAIN_AUX_D) | \
> - BIT(POWER_DOMAIN_INIT))
> -
> -#define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
> - BIT(POWER_DOMAIN_AUX_D) | \
> - BIT(POWER_DOMAIN_INIT))
> -
> static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
> .sync_hw = i9xx_always_on_power_well_noop,
> .enable = i9xx_always_on_power_well_noop,
> @@ -1428,40 +1405,17 @@ static struct i915_power_well chv_power_wells[] = {
> .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
> .ops = &i9xx_always_on_power_well_ops,
> },
> -#if 0
> {
> .name = "display",
> - .domains = VLV_DISPLAY_POWER_DOMAINS,
> - .data = PUNIT_POWER_WELL_DISP2D,
> - .ops = &vlv_display_power_well_ops,
> - },
> -#endif
> - {
> - .name = "pipe-a",
> /*
> - * FIXME: pipe A power well seems to be the new disp2d well.
> - * At least all registers seem to be housed there. Figure
> - * out if this a a temporary situation in pre-production
> - * hardware or a permanent state of affairs.
> + * Pipe A power well is the new disp2d well. Pipe B and C
> + * power wells don't actually exist. Pipe A power well is
> + * required for any pipe to work.
> */
> - .domains = CHV_PIPE_A_POWER_DOMAINS | VLV_DISPLAY_POWER_DOMAINS,
> + .domains = VLV_DISPLAY_POWER_DOMAINS,
> .data = PIPE_A,
> .ops = &chv_pipe_power_well_ops,
> },
> -#if 0
> - {
> - .name = "pipe-b",
> - .domains = CHV_PIPE_B_POWER_DOMAINS,
> - .data = PIPE_B,
> - .ops = &chv_pipe_power_well_ops,
> - },
> - {
> - .name = "pipe-c",
> - .domains = CHV_PIPE_C_POWER_DOMAINS,
> - .data = PIPE_C,
> - .ops = &chv_pipe_power_well_ops,
> - },
> -#endif
> {
> .name = "dpio-common-bc",
> .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
> @@ -1474,50 +1428,6 @@ static struct i915_power_well chv_power_wells[] = {
> .data = PUNIT_POWER_WELL_DPIO_CMN_D,
> .ops = &chv_dpio_cmn_power_well_ops,
> },
> -#if 0
> - {
> - .name = "dpio-tx-b-01",
> - .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
> - VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
> - .ops = &vlv_dpio_power_well_ops,
> - .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
> - },
> - {
> - .name = "dpio-tx-b-23",
> - .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
> - VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
> - .ops = &vlv_dpio_power_well_ops,
> - .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
> - },
> - {
> - .name = "dpio-tx-c-01",
> - .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
> - VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
> - .ops = &vlv_dpio_power_well_ops,
> - .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
> - },
> - {
> - .name = "dpio-tx-c-23",
> - .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
> - VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
> - .ops = &vlv_dpio_power_well_ops,
> - .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
> - },
> - {
> - .name = "dpio-tx-d-01",
> - .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
> - CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
> - .ops = &vlv_dpio_power_well_ops,
> - .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_01,
> - },
> - {
> - .name = "dpio-tx-d-23",
> - .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
> - CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
> - .ops = &vlv_dpio_power_well_ops,
> - .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_23,
> - },
> -#endif
> };
>
> static struct i915_power_well *lookup_power_well(struct drm_i915_private
> *dev_priv,
> --
> 2.3.6
>
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> [email protected]
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--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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