On 5/5/2015 9:14 PM, Imre Deak wrote:
On ma, 2015-05-04 at 20:50 +0530, Vandana Kannan wrote:BUN 1: prop_coeff, int_coeff, tdctargetcnt programming updated and tied to VCO frequencies. Program i_lockthresh in PORT_PLL_9. VCO calculated based on the formula: Desired Output = Port bit rate in MHz (DisplayPort HBR2 is 5400 MHz) Fast Clock = Desired Output / 2 VCO = Fast Clock * P1 * P2 Prop_coeff, int_coeff, and tdctargetcnt modified according to above calculation. BUN 2: Port PLLs require additional programming at certain frequencies - DCO amplitude in PORT_PLL_10 Review comments from Siva which were addressed in the initial version of the patch. - Change PORT_PLL_LOCK_THRESHOLD to PORT_PLL_LOCK_THRESHOLD_MASK - Calculate for HDMI - Correct values for vco = 5.4 - return in case of invalid vco range Signed-off-by: Vandana Kannan <[email protected]> Cc: Sivakumar Thulasimani <[email protected]> --- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/i915_reg.h | 6 ++++ drivers/gpu/drm/i915/intel_ddi.c | 72 +++++++++++++++++++++++++++++++--------- 3 files changed, 63 insertions(+), 17 deletions(-)
[...]
/* Recalibrate with new settings */ temp = I915_READ(BXT_PORT_PLL_EBB_4(port)); @@ -2415,6 +2454,7 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3)); hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6)); hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8)); + hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10)); /* * While we write to the group register to program all lanes at once we * can read only lane registers. We configure all lanes the same way, soWe should also read out pll10 in bxt_ddi_pll_get_hw_state() for consistency.
I have added a readout above for pll10 or am I missing something ? Agree with all other comments, will resend the patch with the changes made. - Vandana
--Imre
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