From: Ville Syrjälä <[email protected]> We currently lack the code to enable CxSR on 85x. The hardware seems to have a few different SR modes, but let's ust use the most straightforward one and hope this saves a bit of extra power.
I haven't observed any ill effects with this enabled on my 855. Signed-off-by: Ville Syrjälä <[email protected]> --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b522eb6..45308c7 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1498,6 +1498,7 @@ enum skl_disp_power_wells { #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ #define MI_STATE 0x020e4 /* gen2 only */ +#define MI_SR_EN (3 << 3) /* 85x only */ #define MI_AGPBUSY_INT_EN (1 << 1) /* 85x only */ #define MI_AGPBUSY_830_MODE (1 << 0) /* 85x only */ diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index fa4ccb3..d23fb82 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -327,6 +327,10 @@ void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable) val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) : _MASKED_BIT_DISABLE(INSTPM_SELF_EN); I915_WRITE(INSTPM, val); + } else if (IS_I85X(dev)) { + val = enable ? _MASKED_BIT_ENABLE(MI_SR_EN) : + _MASKED_BIT_DISABLE(MI_SR_EN); + I915_WRITE(MI_STATE, val); } else { return; } -- 2.0.5 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
