On Wed, Jan 21, 2015 at 06:50:41PM +0000, Siluvery, Arun wrote: > On 21/01/2015 17:37, [email protected] wrote: > >From: Ville Syrjälä <[email protected]> > > > >Wa4x4STCOptimizationDisable got only implemented for BDW, but according > >to the w/a database CHV needs it too, so add it. > > > >Signed-off-by: Ville Syrjälä <[email protected]> > >--- > > drivers/gpu/drm/i915/intel_ringbuffer.c | 4 ++++ > > 1 file changed, 4 insertions(+) > > > >diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c > >b/drivers/gpu/drm/i915/intel_ringbuffer.c > >index d7aa5c4..2a1a178 100644 > >--- a/drivers/gpu/drm/i915/intel_ringbuffer.c > >+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > >@@ -851,6 +851,10 @@ static int chv_init_workarounds(struct intel_engine_cs > >*ring) > > */ > > WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); > > > >+ /* Wa4x4STCOptimizationDisable:chv */ > >+ WA_SET_BIT_MASKED(CACHE_MODE_1, > >+ GEN8_4x4_STC_OPTIMIZATION_DISABLE); > >+ > > /* Improve HiZ throughput on CHV. */ > > WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); > > > > > Looks good to me. > only tested Wa4x4STCOptimizationDisable on Android, no issues observed. > > For the whole series, > Reviewed-by: Arun Siluvery <[email protected]>
All merged, thanks. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
