On Thu, 04 Dec 2014, Gaurav K Singh <[email protected]> wrote: > For Dual link MIPI Panels, dsipll clock for both DSI0 and DSI1 needs to be > enabled. > > v2: Address review comments by Jani > - Added wait time for PLL to be locked. > > v3: separate patch created for cck read for checking PLL to be locked > > Signed-off-by: Gaurav K Singh <[email protected]> > Signed-off-by: Shobhit Kumar <[email protected]>
Reviewed-by: Jani Nikula <[email protected]> > --- > drivers/gpu/drm/i915/intel_dsi_pll.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c > b/drivers/gpu/drm/i915/intel_dsi_pll.c > index fa7a6ca..636d72f 100644 > --- a/drivers/gpu/drm/i915/intel_dsi_pll.c > +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c > @@ -243,6 +243,9 @@ static void vlv_configure_dsi_pll(struct intel_encoder > *encoder) > > dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL; > > + if (intel_dsi->dual_link) > + dsi_mnp.dsi_pll_ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL; > + > DRM_DEBUG_KMS("dsi pll div %08x, ctrl %08x\n", > dsi_mnp.dsi_pll_div, dsi_mnp.dsi_pll_ctrl); > > -- > 1.7.9.5 > > _______________________________________________ > Intel-gfx mailing list > [email protected] > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
