On Sat, 28 Jun 2014 02:04:03 +0300 [email protected] wrote: > From: Ville Syrjälä <[email protected]> > > CHV display PHY registes have two swing margin/deemph settings. Make it > clear which ones we're using. > > Signed-off-by: Ville Syrjälä <[email protected]> > --- > drivers/gpu/drm/i915/i915_reg.h | 8 ++++++-- > drivers/gpu/drm/i915/intel_dp.c | 4 ++-- > drivers/gpu/drm/i915/intel_hdmi.c | 4 ++-- > 3 files changed, 10 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index e296312..ba90320 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -831,8 +831,8 @@ enum punit_power_well { > > #define _VLV_TX_DW2_CH0 0x8288 > #define _VLV_TX_DW2_CH1 0x8488 > -#define DPIO_SWING_MARGIN_SHIFT 16 > -#define DPIO_SWING_MARGIN_MASK (0xff << DPIO_SWING_MARGIN_SHIFT) > +#define DPIO_SWING_MARGIN000_SHIFT 16 > +#define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT) > #define DPIO_UNIQ_TRANS_SCALE_SHIFT 8 > #define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1) > > @@ -840,12 +840,16 @@ enum punit_power_well { > #define _VLV_TX_DW3_CH1 0x848c > /* The following bit for CHV phy */ > #define DPIO_TX_UNIQ_TRANS_SCALE_EN (1<<27) > +#define DPIO_SWING_MARGIN101_SHIFT 16 > +#define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT) > #define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1) > > #define _VLV_TX_DW4_CH0 0x8290 > #define _VLV_TX_DW4_CH1 0x8490 > #define DPIO_SWING_DEEMPH9P5_SHIFT 24 > #define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT) > +#define DPIO_SWING_DEEMPH6P0_SHIFT 16 > +#define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT) > #define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1) > > #define _VLV_TX3_DW4_CH0 0x690 > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index e272f92..4457f8f 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -2565,8 +2565,8 @@ static uint32_t intel_chv_signal_levels(struct intel_dp > *intel_dp) > /* Program swing margin */ > for (i = 0; i < 4; i++) { > val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); > - val &= ~DPIO_SWING_MARGIN_MASK; > - val |= margin_reg_value << DPIO_SWING_MARGIN_SHIFT; > + val &= ~DPIO_SWING_MARGIN000_MASK; > + val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT; > vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); > } > > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c > b/drivers/gpu/drm/i915/intel_hdmi.c > index c9d77d3..c5c88127 100644 > --- a/drivers/gpu/drm/i915/intel_hdmi.c > +++ b/drivers/gpu/drm/i915/intel_hdmi.c > @@ -1411,8 +1411,8 @@ static void chv_hdmi_pre_enable(struct intel_encoder > *encoder) > > for (i = 0; i < 4; i++) { > val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); > - val &= ~DPIO_SWING_MARGIN_MASK; > - val |= 102 << DPIO_SWING_MARGIN_SHIFT; > + val &= ~DPIO_SWING_MARGIN000_MASK; > + val |= 102 << DPIO_SWING_MARGIN000_SHIFT; > vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); > } >
Reviewed-by: Jesse Barnes <[email protected]> -- Jesse Barnes, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
