On Fri, 13 Jun 2014 13:37:52 +0300 [email protected] wrote: > From: Ville Syrjälä <[email protected]> > > VLV Punit doesn't support the 400MHz cdclk option, so we bypass the > Punit and poke at CCK directly. However we forgot to wait for the > frequeency change to complete. Poll the CCK clock status to make sure > the clock has changed before we fire up any pipes. > > Signed-off-by: Ville Syrjälä <[email protected]> > --- > drivers/gpu/drm/i915/intel_display.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index 3a9b017..29dddec 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -4483,6 +4483,11 @@ static void valleyview_set_cdclk(struct drm_device > *dev, int cdclk) > val &= ~DISPLAY_FREQUENCY_VALUES; > val |= divider; > vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); > + > + if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) > & > + DISPLAY_FREQUENCY_STATUS) == (divider << > DISPLAY_FREQUENCY_STATUS_SHIFT), > + 50)) > + DRM_ERROR("timed out waiting for CDclk change\n"); > mutex_unlock(&dev_priv->dpio_lock); > } >
Seems reasonable, assuming this actually works in testing. Reviewed-by: Jesse Barnes <[email protected]> -- Jesse Barnes, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
