From: Ville Syrjälä <[email protected]> 915/945 have the same reset registers as 965, so share the code.
Signed-off-by: Ville Syrjälä <[email protected]> --- drivers/gpu/drm/i915/i915_drv.c | 3 ++- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_uncore.c | 26 ++++++++++++++------------ 3 files changed, 17 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 2ec3796..187f42c 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -794,7 +794,8 @@ int i915_reset(struct drm_device *dev) if (INTEL_INFO(dev)->gen > 5) intel_reset_gt_powersave(dev); - if (IS_GEN4(dev) && !IS_G4X(dev)) { + if ((IS_GEN3(dev) && !IS_G33(dev)) || + (IS_GEN4(dev) && !IS_G4X(dev))) { intel_init_clock_gating(dev); drm_modeset_lock_all(dev); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 1346c1e..018fd9d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -78,7 +78,7 @@ /* Graphics reset regs */ -#define I965_GDRST 0xc0 /* PCI config register */ +#define I915_GDRST 0xc0 /* PCI config register */ #define GRDOM_FULL (0<<2) #define GRDOM_RENDER (1<<2) #define GRDOM_MEDIA (3<<2) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index f073fa0..a043baf 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -956,27 +956,27 @@ int i915_get_reset_stats_ioctl(struct drm_device *dev, return 0; } -static int i965_reset_complete(struct drm_device *dev) +static int i915_reset_complete(struct drm_device *dev) { u8 gdrst; - pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); + pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst); return (gdrst & GRDOM_RESET_STATUS) == 0; } -static int i965_do_reset(struct drm_device *dev) +static int i915_do_reset(struct drm_device *dev) { /* assert reset for at least 20 usec */ - pci_write_config_byte(dev->pdev, I965_GDRST, GRDOM_RESET_ENABLE); + pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE); udelay(20); - pci_write_config_byte(dev->pdev, I965_GDRST, 0); + pci_write_config_byte(dev->pdev, I915_GDRST, 0); - return wait_for(i965_reset_complete(dev), 500); + return wait_for(i915_reset_complete(dev), 500); } static int g4x_reset_complete(struct drm_device *dev) { u8 gdrst; - pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); + pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst); return (gdrst & GRDOM_RESET_ENABLE) == 0; } @@ -985,7 +985,7 @@ static int g4x_do_reset(struct drm_device *dev) struct drm_i915_private *dev_priv = dev->dev_private; int ret; - pci_write_config_byte(dev->pdev, I965_GDRST, + pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RENDER | GRDOM_RESET_ENABLE); ret = wait_for(g4x_reset_complete(dev), 500); if (ret) @@ -995,7 +995,7 @@ static int g4x_do_reset(struct drm_device *dev) I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE); POSTING_READ(VDECCLK_GATE_D); - pci_write_config_byte(dev->pdev, I965_GDRST, + pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_MEDIA | GRDOM_RESET_ENABLE); ret = wait_for(g4x_reset_complete(dev), 500); if (ret) @@ -1005,7 +1005,7 @@ static int g4x_do_reset(struct drm_device *dev) I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE); POSTING_READ(VDECCLK_GATE_D); - pci_write_config_byte(dev->pdev, I965_GDRST, 0); + pci_write_config_byte(dev->pdev, I915_GDRST, 0); return 0; } @@ -1065,8 +1065,10 @@ int intel_gpu_reset(struct drm_device *dev) case 4: if (IS_G4X(dev)) return g4x_do_reset(dev); - else - return i965_do_reset(dev); + case 3: + if (IS_G33(dev)) + return -ENODEV; + return i915_do_reset(dev); default: return -ENODEV; } } -- 1.8.5.5 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
