> -----Original Message-----
> From: Dibin Moolakadan Subrahmanian
> <[email protected]>
> Sent: Friday, June 5, 2026 2:14 PM
> To: [email protected]; [email protected]
> Cc: Manna, Animesh <[email protected]>; Shankar, Uma
> <[email protected]>; [email protected]
> Subject: [PATCH v5 14/14] drm/i915/display: Add DC3CO count and residency in
> dmc debugfs
>
> Expose DC3CO count and residency for xe3lp platforms via debugfs.
>
> Changes in v4:
> - Keep dc5_reg register initialization to avoid any
> invalid access (sashiko)
>
> Changes in v5:
> - Change XE3P_DMC_DC3CO_COUNT address to lower case (Manna Animesh).
Looks Good to me.
Reviewed-by: Uma Shankar <[email protected]>
> Signed-off-by: Dibin Moolakadan Subrahmanian
> <[email protected]>
> ---
> drivers/gpu/drm/i915/display/intel_dmc.c | 9 ++++++++-
> drivers/gpu/drm/i915/display/intel_dmc_regs.h | 2 ++
> 2 files changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
> b/drivers/gpu/drm/i915/display/intel_dmc.c
> index a133785c815b..5ffe2b1c3c51 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -1650,7 +1650,14 @@ static int intel_dmc_debugfs_status_show(struct
> seq_file *m, void *unused)
> DMC_VERSION_MINOR(dmc->version));
>
> if (DISPLAY_VER(display) >= 12) {
> - if (display->platform.dgfx || DISPLAY_VER(display) >= 14) {
> + if (DISPLAY_VER(display) >= 35) {
> + dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
> + seq_printf(m, "DC3CO count: %d\n",
> + intel_de_read(display,
> XE3P_DMC_DC3CO_COUNT));
> +
> + seq_printf(m, "DC3CO residency: %d\n",
> + intel_de_read(display,
> DC_STATE_DC3CO_RESIDENCY));
> + } else if (display->platform.dgfx || DISPLAY_VER(display) >=
> 14) {
> dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
> } else {
> dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> index 38e342b45af0..6b7978fb8986 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> @@ -531,6 +531,8 @@ enum pipedmc_event_id {
> #define TGL_DMC_DEBUG3 _MMIO(0x101090)
> #define DG1_DMC_DEBUG3 _MMIO(0x13415c)
>
> +#define XE3P_DMC_DC3CO_COUNT _MMIO(0x8f05c)
> +
> #define DMC_WAKELOCK_CFG _MMIO(0x8F1B0)
> #define DMC_WAKELOCK_CFG_ENABLE REG_BIT(31)
> #define DMC_WAKELOCK1_CTL _MMIO(0x8F140)
> --
> 2.43.0
